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maxim integrated products inc. 120 san gabriel drive, sunnyvale ca 94086 19-4572; rev 0; 4/09 product specification crimzon ? infrared microcontrollers zlf645 series flash mcuswith learning amplification downloaded from: http:///
19-4572; rev 0; 4/09 maxim integrated products 120 san gabriel drive sunnyvale, ca 94086 united states 408-737-7600 ? www.maxim-ic.com copyright ? 2009 maxim integrated products maxim cannot assume responsibility for use of any circuitry other than circuitry ent irely embodied in a maxim product. maxim re tains the right to make change s to its products or specifications to improve performance, reliability or manufacturability. all infor mation in this document, includin g descriptions of f eatures, functio ns, per formance, technical specifications and avai lability, is subjec t to change without notice at any time. while the information furnished herein is held to be accurate and reliable, no responsibilit y will be assumed by maxim for its use. f urthermore, the information contained her ein does not c onvey to the pur chaser of micr oelectronic devices any license under the pat ent right of any manufacturer. maxim is a registered trademark of maxim integrated products, inc. all other products or service names used in this publication are for identification purposes only, and may be trademarks or reg istered trademarks of their respective companies. all other trademarks or registered tr ademarks mentioned he rein are th e property of th eir respective holders. z8 is a registered trademark of zilog, inc. crimzon is a registered trademark of universal electronics inc. downloaded from: http:///
19-4572; rev 0; 4/09 revision history zlf645 series flash mcus product specification iii revision history each instance in the revision history table re flects a change to this document from its pre- vious revision. for more details, refer to the corresponding pages or appropriate links given in the table below. date version description page number december 2008 08 updated formula in flash controller section. updated v lvd in table 80 and v flpe in table 82 in electrical characteristics section. updated table 56 through table 59 in timers section. added flash programming through the icp interface in icp interface section. added using the watchdog time r as a stop mode recovery source in reset and power management section. updated flash frequency high and low byte registers section and table 83 . ? updated port 1 pins in figure 1 . 67 165 , 170 119 61 142 79 , 172 4 april 2008 07 updated enabling the flash byte programming interface section. 82 april 2008 06 deleted design info subs ection and all of its associated text. updated flash memory overview section; updated figure 19 . updated flash frequency high and low byte registers section. updated icc and icc1 in table 80 . updated notes in table 5 and table 6 . removed preliminary and precharacterization product notice. added 20-pin qfn package to pin description , table 3 , table 4 , packaging , table 87 , and part number description . change p31 to p32 at the beginning of universal asynchronous receiver/transmitter . all 67 , 68 79 165 9 , 10 all 5 , 6 , 7 , 17 6 , 184 , 186 85 january 2008 05 updated flash code protection against external access and flash frequency high and low byte registers . 73 , 79 january 2008 04 chapter reset and power management : updated table 68 . 142 downloaded from: http:///
19-4572; rev 0; 4/09 able of contentstable able of table table of contents zlf645 series flash mcus product specification iv table of contents architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 i/o port pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 reset (input, active low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 comparator inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 comparator outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 port configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 port 0/1 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 port 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 port 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 port 2 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 port 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 port 3 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 port 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 port 4 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 port 4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 memory and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 flash program/constant memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 register pointer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 linear memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 register pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 stack pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 downloaded from: http:///
19-4572; rev 0; 4/09 able of contentstable able of table table of contents zlf645 series flash mcus product specification v register file summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 icp interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 enabling icp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 state of zlf645 in icp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 enabling flash accesses through the icp . . . . . . . . . . . . . . . . . . . . . . . . . 54 icp interface logic architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 icp interface operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 icp data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 icp auto-baud detector/generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 icp serial errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 icp in-circuit programming commands . . . . . . . . . . . . . . . . . . . . . . . . . . 57 flash programming through the icp interface . . . . . . . . . . . . . . . . . . . . . . 61 differences between cpu based and icp based flash programming/ erase access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 using icp commands for flash program ming/read operations . . . . . 61 in-circuit programming control register defini tions . . . . . . . . . . . . . . . . . . 64 icp control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 icp status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 test mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 exiting icp mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 flash information block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 flash controller overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 executing flash memory accesses thr ough the flash controller . . . . 69 flash code protection against external access . . . . . . . . . . . . . . . . . . 73 flash code protection against accidental program and erasure . . . . . 73 byte programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 page erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 mass erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 flash control register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 flash status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 flash page select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 flash sector protect register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 flash frequency high and low byte registers . . . . . . . . . . . . . . . . . . 79 flash controller functions summary . . . . . . . . . . . . . . . . . . . . . . . . . . 80 flash byte programming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 downloaded from: http:///
19-4572; rev 0; 4/09 able of contentstable able of table table of contents zlf645 series flash mcus product specification vi enabling the flash byte programming interface . . . . . . . . . . . . . . . . . . . . 82 flash byte programming interface flash access restrictions . . . . . . . . . . 82 infrared learning amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 universal asynchronous receiver/transmitter . . . . . . . . . . . . . . . . . . . . . . 85 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 transmitting data using polled method . . . . . . . . . . . . . . . . . . . . . . . . 87 transmitting data using interrupt-driven method . . . . . . . . . . . . . . . . . 88 receiving data using the polled method . . . . . . . . . . . . . . . . . . . . . . . 89 receiving data using the interrupt-driven method . . . . . . . . . . . . . . . . 89 uart interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 uart baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 uart receive data register/uart transmit data register . . . . . . . . . . . 95 uart status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 uart control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 uart baud rate generator constant register . . . . . . . . . . . . . . . . . . . . . 97 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 counter/timer functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 t8 transmit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 t8 demodulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 t16 transmit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 t16 demodulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 ping-pong mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 timer output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 counter/timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 timer 8 capture high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 timer 8 capture low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 timer 16 capture high register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 timer 16 capture low register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 counter/timer 16 high hold register . . . . . . . . . . . . . . . . . . . . . . . . . 116 counter/timer 16 low hold register . . . . . . . . . . . . . . . . . . . . . . . . . 117 counter/timer 8 high hold register . . . . . . . . . . . . . . . . . . . . . . . . . . 117 counter/timer 8 low hold register . . . . . . . . . . . . . . . . . . . . . . . . . . 118 counter/timer 8 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 t8 and t16 common functions register . . . . . . . . . . . . . . . . . . . . . . 121 counter/timer 16 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 timer 8/timer 16 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 downloaded from: http:///
19-4572; rev 0; 4/09 able of contentstable able of table table of contents zlf645 series flash mcus product specification vii interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 interrupt priority register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 interrupt request register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 interrupt mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 crystal 1 oscillator pin (xtal1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 crystal 2 oscillator pin (xtal2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 internal clock signals (sclk and tclk) . . . . . . . . . . . . . . . . . . . . . . . . . 135 reset and power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 voltage brownout standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 power-on reset timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 using the watchdog timer as a stop mode recovery source . . . . . . 142 reset/stop mode recovery status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 fast stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 stop mode recovery interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 stop mode recovery event sources . . . . . . . . . . . . . . . . . . . . . . . . . . 144 smr register events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 smr1 register events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 smr2 register events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 smr3 register events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 stop mode recovery register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 z8 lxmc cpu programming summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 addressing notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 flags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 condition codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 flash option bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 downloaded from: http:///
19-4572; rev 0; 4/09 able of contentstable able of table table of contents zlf645 series flash mcus product specification viii operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 option bit shadow register loading by reset . . . . . . . . . . . . . . . . . . 171 user option bit locations in flash memory . . . . . . . . . . . . . . . . . . . . 172 user option bit shadow register access . . . . . . . . . . . . . . . . . . . . . . 172 user option byte 0 and option byte 0 shadow ? register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 72 user option byte 1 and opti on byte 1 shadow register ? definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 part number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 downloaded from: http:///
ps026408-1208 architectural overview zlf645 series flash mcus product specification 1 architectural overview maxims zlf645 series of flash mcus are members of the crimzon ? family of infrared microcontrollers. this series provides a dire ctly-compatible code upgrade path to other crimzon mcus, offers a robust learning function, and features up to 64 kb flash memory and 1k general-purpose random access me mory (ram). two timers allow the generation of complex signals while performing other counting operations. a universal asynchronous receiver/transmi tter (uart) allows the zlf645 mcu to function as a slave/master database chip. wh en the uart is not in use, the baud rate generator (brg) can be used as a third timer. enhanc ed stop mode recovery features allow the zlf645 mcu to recover from stop mode on any change of logic and on any combination of the 12 smr inputs. the smr so urce can also be used as an interrupt source. many high-end remote control units offer a learning function. a learning function allows a replacement remote unit to learn infrared signals from the original remote unit and regenerate the signal. however, the amplifyi ng circuits of many learning remotes are expensive and are not tuned we ll. the zlf645 mcu is the first chip to offer a built-in tuned amplification circuit in a wide range of positions an d battery voltages. the only external component required is a photodiode. the zlf645 mcu greatly reduces the system cost and improves learning function reliability. with all new features, the zlf6 45 mcu is excellent for infrared remote ? control and other mcu applications. features table 1 lists the memory, i/o, and power featur es of the zlf645 flash mcu. additional features are listed below the table. table 1. zlf645 flash mcu features device flash (kb) ram* i/o lines voltage range zlf645 flash mcu 32 or 64 512 b or 1 k 16, 24, or 40 2.0 vC3.6 v * general-purpose register s implemented as ram. downloaded from: http:///
ps026408-1208 features zlf645 series flash mcus product specification 2 interrupt sources the zlf645 mcu suppor ts 23 interrupt sources with 6 interrupt vectors, as given below: three external interrupts. two from t8, t16 time-out and capture. three from uart tx, uart rx, and uart brg. one from lvd. fourteen from smr source p20-p27, p30-p33, p00, and p07: C any change in logic from p20-p27, p30-p33 can generate an interrupt or smr ? additional features the additional features of zlf645 mcu include: ir learning amplifier. low power consumption11 mw (typical). three standby modes: C stop1.7 ? a (typical) C halt0.6 ma (typical) C low-voltage reset intelligent counter/timer architecture to automate generation or reception and demodulation of complex waveform, and pulsed signals: C one programmable 8-bit counter/timer with tw o capture registers and two load registers C one programmable 16-bit counte r/timer with one 16-bit capture register pair and one 16-bit load register pair C programmable input glitch filter for pulse reception C the uart baud rate generator can be used as another 8-bit timer, when the uart is not in use six priority interrupts:C three external/uart interrupts C two assigned to counter/timers C one low-voltage detection interrupt downloaded from: http:///
ps026408-1208 features zlf645 series flash mcus product specification 3 8-bit uart:C r x and t x interrupts C 4800, 9600, 19200, and 38400 baud rates C parity odd/even/none C stop bits 1/2 icp (in-circuit flash programming) interf ace multiplexed with one of the gpios. intelligent power-on reset (por) to pr ovide reduced por time on detection ? of stable clock from external crystal oscillator or resonator. low-voltage and high-voltage detection flags. programmable watchdog ti mer (wdt)/por circuits. two on-board analog comparators with independent reference voltages and programmable interrupt polarity. user-selectable options through op tion bit flash coding (on/off): C port 0 pins 0C3 pull-up transistors C port 0 pins 4C7 pull-up transistors C port 1 pins 0C3 pull-up transistors C port 1 pins 4C7 pull-up transistors C port 2 pins 0C7 pull-up transistors C port 3 pins 0C3 pull-up transistors C port 4 pins 0C7 pull-up transistors C wdt enabled at power-on reset C flash lowest half main memory protect C flash entire main memory protect C 16-bit addressability for stack pointer C no division, divide by 2, divide by 16, or divide by 32 of external clock to system clock ? all signals with an overline, , are active low. for example, b/w , in which word is active low, and b /w, in which byte is active low. power connections use the conven tional descriptions listed in table 2 . table 2. power connections connection device power v dd ground v ss note: downloaded from: http:///
ps026408-1208 functional block diagram zlf645 series flash mcus product specification 4 functional block diagram figure 1 displays the functional blocks of the zlf645 flash mcu. figure 1. zlf645 flash mcu functional block diagram port 2 port 0 p21 p22 p23 p24 p25 p26 p27 p20 i/o bit programmable p04 p05 p06 p07 p00p01 p02 p03 i/o nibble programmable register file 512 b/1 k x 8-bit register bus internal address bus internal data bus expanded register file register bus machine timing & instruction control 4 4 flash up to 64 kb x 8-bit port 3 p31p32 p33 p34 p35 p36 p37 p30 z8 ? lxmc core directional directional two comparators low-voltage/ 8-bit timer 8-bit timer 16-bit timer ir learning amplification port 1 port 4 p10 p11 p12 p13 p14 p15 p16 p17 p40 p41 p42 p43 p44 p45p46 p47 8 i/o byte programmable directional fix cmos fix push pull output i/o bit programmable directional with uart power-on reset detection high-voltage input reset xtal2 xtal1 downloaded from: http:///
19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 5 pin description 1617 18 19 15 14 13 12 11 23 4 5 109 8 7 6 figure 2 displays the pin configuration for zlf645 mcu 20-pin qfn packages. figure 2. 20-pin qfn pin configuration downloaded from: http:///
19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 6 table 3 lists the function and signal directions of each pin within the 20-pin qfn package sequentially by pin number. table 3. 20-pin qfn sequential pin identification pin no symbol function signal direction 1 p07 port 0, bit 7 input/output 2v dd power supply input 3 xtal2 crystal oscillator output 4 xtal1 crystal oscillator input 5 p31 port 3, bit 1 input 6 p32 port 3, bit 2 input 7 p33 port 3, bit 3 input 8 p34 port 3, bit 4 input/output 9 p36 port 3, bit 6 output 10 p00 port 0, bit 0 input/output p30 port 3, bit 0 input 11 p01 port 0, bit 1 input/output 12 gnd ground in put 13 p20 port 2, bit 0 input/output 14 p21 port 2, bit 1 input/output 15 p22 port 2, bit 2 input/output 16 p23 port 2, bit 3 input/output 17 p24 port 2, bit 4 input/output 18 p25 port 2, bit 5 input/output 19 p26 port 2, bit 6 input/output 20 p27 port 2, bit 7 input/output note: when the port 0 low-nibble pull-up option is enabled and the p30 input is low, current flows through the pull-up to ground. downloaded from: http:///
19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 7 table 4 lists the function and signal direction of each pin within the 20-pin qfn package by function. table 4. 20-pin qfn functional pin identification pin no symbol function signal direction 10 p00 port 0, bit 0 input/output p30 port 3, bit 0 input 11 p01 port 0, bit 1 input/output 1 p07 port 0, bit 7 input/output 13 p20 port 2, bit 0 input/output 14 p21 port 2, bit 1 input/output 15 p22 port 2, bit 2 input/output 16 p23 port 2, bit 3 input/output 17 p24 port 2, bit 4 input/output 18 p25 port 2, bit 5 input/output 19 p26 port 2, bit 6 input/output 20 p27 port 2, bit 7 input/output 5 p31 port 3, bit 1 input 6 p32 port 3, bit 2 input 7 p33 port 3, bit 3 input 8 p34 port 3, bit 4 input/output 9 p36 port 3, bit 6 output 2v dd power supply input 12 gnd ground in put 4 xtal1 crystal oscillator input 3 xtal2 crystal oscillator output note: when the port 0 low-nibble pull-up option is e nabled and the p30 input is low, current flows through the pull-up to ground. downloaded from: http:///
19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 8 figure 3 displays the pin configuration for z lf645 mcu 20-pin pdip, soic, and ssop packages. figure 3. 20-pin pdip/soic/ ssop pin configuration p25p26 p27 p07 v dd xtal2 xtal1 p31p32 p33 p24p23 p22 p21 p20 v ss p01p00/p30 p36 p34 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 13 12 11 20-pin pdip soic ssop downloaded from: http:///
19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 9 table 5 lists the function and signal directions of each pin within the 20-pin pdip, soic, and ssop packages sequentially by pin number. table 5. 20-pin pdip/soic/ssop sequential pin identification pin no symbol function signal direction 1 p25 port 2, bit 5 input/output 2 p26 port 2, bit 6 input/output 3 p27 port 2, bit 7 input/output 4 p07 port 0, bit 7 input/output 5v dd power supply input 6 xtal2 crystal oscillator output 7 xtal1 crystal oscillator input 8 p31 port 3, bit 1 input 9 p32 port 3, bit 2 input 10 p33 port 3, bit 3 input 11 p34 port 3, bit 4 input/output 12 p36 port 3, bit 6 output 13 p00 port 0, bit 0 input/output p30 port 3, bit 0 input 14 p01 port 0, bit 1 input/output 15 v ss ground in put 16 p20 port 2, bit 0 input/output 17 p21 port 2, bit 1 input/output 18 p22 port 2, bit 2 input/output 19 p23 port 2, bit 3 input/output 20 p24 port 2, bit 4 input/output note: when the port 0 low-nibble pull-up option is enabled and the p30 input is low, current flows through the pull-up to ground. downloaded from: http:///
19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 10 table 6 lists the function and signal direction of each pin within the 20-pin pdip, soic, and ssop packages by function. table 6. 20-pin pdip/soic/ssop functional pin identification pin no symbol function signal direction 13 p00 port 0, bit 0 input/output p30 port 3, bit 0 input 14 p01 port 0, bit 1 input/output 4 p07 port 0, bit 7 input/output 16 p20 port 2, bit 0 input/output 17 p21 port 2, bit 1 input/output 18 p22 port 2, bit 2 input/output 19 p23 port 2, bit 3 input/output 20 p24 port 2, bit 4 input/output 1 p25 port 2, bit 5 input/output 2 p26 port 2, bit 6 input/output 3 p27 port 2, bit 7 input/output 8 p31 port 3, bit 1 input 9 p32 port 3, bit 2 input 10 p33 port 3, bit 3 input 11 p34 port 3, bit 4 input/output 12 p36 port 3, bit 6 output 5v dd power supply input 15 v ss ground in put 7 xtal1 crystal oscillator input 6 xtal2 crystal oscillator output note: when the port 0 low-nibble pull-up option is e nabled and the p30 input is low, current flows through the pull-up to ground. downloaded from: http:///
19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 11 figure 4 displays the pin configuration of the zlf645 mcu within the 28-pin pdip, soic, and ssop packages. figure 4. 28-pin pdip/soic/ ssop pin configuration p24p23 p22 p21 p20 p03 v ss p02p01 p00 p30 p36 p37 p35 p25p26 p27 p04 p05 p06 p07 v dd xtal2 xtal1 p31p32 p33 p34 1 28-pin pdip soic ssop 23 4 5 6 7 8 9 10 11 12 13 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 downloaded from: http:///
19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 12 table 7 lists the function and signal directions of each pin within the 28-pin pdip, soic, and ssop packages sequentially by pin number. table 7. 28-pin pdip/soic/ssop sequential pin identification pin no symbol function signal direction 1 p25 port 2, bit 5 input/output 2 p26 port 2, bit 6 input/output 3 p27 port 2, bit 7 input/output 4 p04 port 0, bit 4 input/output 5 p05 port 0, bit 5 input/output 6 p06 port 0, bit 6 input/output 7 p07 port 0, bit 7 input/output 8v dd power supply input 9 xtal2 crystal oscillator output 10 xtal1 crystal oscillator input 11 p31 port 3, bit 1 input 12 p32 port 3, bit 2 input 13 p33 port 3, bit 3 input 14 p34 port 3, bit 4 input/output 15 p35 port 3, bit 5 output 16 p37 port 3, bit 7 output 17 p36 port 3, bit 6 output 18 p30 port 3, bit 0; connect to vdd if not used input 19 p00 port 0, bit 0 input/output 20 p01 port 0, bit 1 input/output 21 p02 port 0, bit 2 input/output 22 v ss ground input 23 p03 port 0, bit 3 input/output 24 p20 port 2, bit 0 input/output 25 p21 port 2, bit 1 input/output 26 p22 port 2, bit 2 input/output 27 p23 port 2, bit 3 input/output 28 p24 port 2, bit 4 input/output downloaded from: http:///
19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 13 table 8 lists the functions and signal directions of each pin within the 28-pin pdip, soic, and ssop packages by function. table 8. 28-pin pdip/soic/ssop functional pin identification pin no symbol function signal direction 19 p00 port 0, bit 0 input/output 20 p01 port 0, bit 1 input/output 21 p02 port 0, bit 2 input/output 23 p03 port 0, bit 3 input/output 4 p04 port 0, bit 4 input/output 5 p05 port 0, bit 5 input/output 6 p06 port 0, bit 6 input/output 7 p07 port 0, bit 7 input/output 24 p20 port 2, bit 0 input/output 25 p21 port 2, bit 1 input/output 26 p22 port 2, bit 2 input/output 27 p23 port 2, bit 3 input/output 28 p24 port 2, bit 4 input/output 1 p25 port 2, bit 5 input/output 2 p26 port 2, bit 6 input/output 3 p27 port 2, bit 7 input/output 18 p30 port 3, bit 0; connect to vdd if not used input 11 p31 port 3, bit 1 input 12 p32 port 3, bit 2 input 13 p33 port 3, bit 3 input 14 p34 port 3, bit 4 input/output 15 p35 port 3, bit 5 output 17 p36 port 3, bit 6 output 16 p37 port 3, bit 7 output 8v dd power supply input 22 v ss ground input 10 xtal1 crystal oscillator input 9 xtal2 crystal oscillator output downloaded from: http:///
p46 p24p23 p22 p21 p20 p03 p13 p12 v ss v ss p45 p02 48-pin ssop p47 p10 p01p00 p44 p30/pref1 p36 p37 p35 /reset p11 4835 4746 45 44 43 42 41 4039 3837 36 3433 32 31 30 29 28 27 26 25 p40p25 p26 p27 p04 p41 p05 p06p14 p15 p07 v dd v dd p42 p16p17 xtal2 xtal1 p31p32 p33 p34 p43 v ss 1 14 23 45 6 7 8 9 10 11 1213 24 15 16 1718 19 2021 2223 19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 14 figure 5 displays the pin configuration of the zlf645 mcu within the 48-pin ssop package. figure 5. 48-pin ssop pin configuration table 9 lists the functions and signal directions of each pin within the 48-pin ssop ? package sequentially by pin number. table 9. 48-pin ssop sequential pin identification pin no symbol function signal direction 1 p40 port 4, bit 0 input/output 2 p25 port 2, bit 5 input/output 3 p26 port 2, bit 6 input/output 4 p27 port 2, bit 7 input/output 5 p04 port 0, bit 4 input/output 6 p41 port 4, bit 1 input/output 7 p05 port 0, bit 5 input/output downloaded from: http:///
19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 15 8 p06 port 0, bit 6 input/output 9 p14 port 1, bit 4 input/output 10 p15 port 1, bit 5 input/output 11 p07 port 0, bit 7 input/output 12 v dd power supply input 13 v dd power supply input 14 p42 port 4, bit 2 input/output 15 p16 port 1, bit 6 input/output 16 p17 port 1, bit 7 input/output 17 xtal2 crystal oscillator output 18 xtal1 crystal oscillator input 19 p31 port 3, bit 1 input 20 p32 port 3, bit 2 input 21 p33 port 3, bit 3 input 22 p34 port 3, bit 4 input/output 23 p43 port 4, bit 3 input/output 24 v ss ground input 25 /reset bidirectional reset signal input/output 26 p35 port 3, bit 5 output 27 p37 port 3, bit 7 output 28 p36 port 3, bit 6 output 29 p30/pref1 port 3, bit 0 input 30 p44 port 4, bit 4 input/output 31 p00 port 0, bit 0 input/output 32 p01 port 0, bit 1 input/output 33 p10 port 1, bit 0 input/output 34 p11 port 1, bit 1 input/output 35 p02 port 0, bit 2 input/output 36 p45 port 4, bit 5 input/output 37 v ss ground input 38 v ss ground input 39 p12 port 1, bit 2 input/output 40 p13 port 1, bit 3 input/output table 9. 48-pin ssop sequential pin identification (continued) pin no symbol function signal direction downloaded from: http:///
19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 16 table 10 lists the functions and signal directions of each pin within the 48-pin ssop ? package by function. 41 p03 port 0, bit 3 input/output 42 p20 port 2, bit 0 input/output 43 p21 port 2, bit 1 input/output 44 p22 port 2, bit 2 input/output 45 p23 port 2, bit 3 input/output 46 p24 port 2, bit 4 input/output 47 p46 port 4, bit 6 input/output 48 p47 port 4, bit 7 input/output table 10. 48-pin ssop functional pin identification pin no symbol function signal direction 31 p00 port 0, bit 0 input/output 32 p01 port 0, bit 1 input/output 35 p02 port 0, bit 2 input/output 41 p03 port 0, bit 3 input/output 5 p04 port 0, bit 4 input/output 7 p05 port 0, bit 5 input/output 8 p06 port 0, bit 6 input/output 11 p07 port 0, bit 7 input/output 33 p10 port 1, bit 0 input/output 34 p11 port 1, bit 1 input/output 39 p12 port 1, bit 2 input/output 40 p13 port 1, bit 3 input/output 9 p14 port 1, bit 4 input/output 10 p15 port 1, bit 5 input/output 15 p16 port 1, bit 6 input/output 16 p17 port 1, bit 7 input/output 42 p20 port 2, bit 0 input/output 43 p21 port 2, bit 1 input/output 44 p22 port 2, bit 2 input/output table 9. 48-pin ssop sequential pin identification (continued) pin no symbol function signal direction downloaded from: http:///
19-4572; rev 0; 4/09 pin description zlf645 series flash mcus product specification 17 45 p23 port 2, bit 3 input/output 46 p24 port 2, bit 4 input/output 2 p25 port 2, bit 5 input/output 3 p26 port 2, bit 6 input/output 4 p27 port 2, bit 7 input/output 29 p30 port 3, bit 0; connect to vdd if not used input 19 p31 port 3, bit 1 input 20 p32 port 3, bit 2 input 21 p33 port 3, bit 3 input 22 p34 port 3, bit 4 input/output 26 p35 port 3, bit 5 output 28 p36 port 3, bit 6 output 27 p37 port 3, bit 7 output 1 p40 port 4, bit 0 input/output 6 p41 port 4, bit 1 input/output 14 p42 port 4, bit 2 input/output 23 p43 port 4, bit 3 input/output 30 p44 port 4, bit 4 input/output 36 p45 port 4, bit 5 input/output 47 p46 port 4, bit 6 input/output 48 p47 port 4, bit 7 input/output 12 v dd power supply input 13 v dd power supply input 24 v ss ground input 37 v ss ground input 38 v ss ground input 18 xtal1 crystal oscillator input 17 xtal2 crystal oscillator output 25 /reset bidirectional reset signal input/output table 10. 48-pin ssop functional pin identification (continued) pin no symbol function signal direction downloaded from: http:///
ps026408-1208 i/o port pin functions zlf645 series flash mcus product specification 18 i/o port pin functions the zlf645 mcu features up to five 8- bit ports which are described below: 1. port 0 is nibble-programmabl e as either input or output. 2. port 1 is byte-programmable as either input or output. 3. port 2 is bit-programmable as either input or output. 4. port 3 features four inputs on the lower nibble and four outputs on the upper nibble. 5. port 4 is bit-programmable as either input or output. port 0, port 1, port 2, and port 4 internal pull-ups are disabled on any pin or group of pins when programmed into output mode. the cmos input buffer for each port 0, port 1, port 2, or port 4 pin are always ? connected to the pin, even when the pin is config ured as an output. if the pin is configured as an open-drain output and no external signal is applied, a high output state can cause the cmos input buffer to float. this may lead to excessive leakage current of more than 100 ? a. to prevent this leakage, connect the pi n to an external signal with a defined logic level or ensure that its output state is low, especially during stop mode. port 0, port 1, port 2, and port 4 have bo th input and output capa bility. the input logic is always present no matter whether the port is configured as in put or output. when ? executing a read instruction, the mcu reads th e actual value at th e input logic but not from the output buffer. in addition, the instructions of or, and, and xor have the read- modify-write sequence. the mcu first reads th e port, then modifies the value, and loads back to the port. precaution must be taken, if the port is configured as an open -drain output or if the port is driving any circuit that ma kes the voltage different from the appropriate output logic. if it is configured as open-drain output with output logic as one, it is a floating port and reads back as zero. the following instruction sets p00Cp07 all low: and p0,#%f0 reset (input, active low) reset initializes the mcu and is accomplished either through power-on reset (por), watchdog timer (wdt), stop mode recovery, low-vo ltage detection, or through the external reset pin in the case of 48-pin packaged products. note: caution: downloaded from: http:///
ps026408-1208 reset (input, active low) zlf645 series flash mcus product specification 19 during por and wdt reset, the internally ge nerated reset drives the reset pin low for the por time. any device driving the external reset line must be open-drain to avoid damage from a possible conflict during reset conditions. a pull-up is provided internally for the reset pin, if available. when the zlf645 mcu asserts (low) the reset pin, the internal pull-up is disabled. the zlf645 mc u does not assert the reset pin when the vdd voltage is below the vbo trip point level (for mo re details, see reset and power management on page 137). the external reset does not initiate an exit from stop mode. table 11 lists the registers used to control i/o po rts. some port pin functions can also be affected by control registers for other peripheral functions. table 11. i/o port control registers address (hex) reset 12-bit bank 8-bit register description mnemonic page no 000 0C3 00 port 0 register p0 xxh 32 001 0C3 01 port 1 register p1 xxh 33 002 0C3 02 port 2 register p2 xxh 35 003 0C3 03 port 3 register p3 0xh 37 f08 0C3 08 port 4 register p4 xxh 40 f09 f 09 port 4 mode register p4m ffh 39 0f6 all f6 port 2 mode register p2m ffh 34 0f7 all f7 port 3 mode register p3m xxxx_x000b 36 0f8 all f8 port 0/1 mode register p01m x1 xx_xxx1b 31 f00 f 00 port configuration register pcon xxxx_1 110b 30 note: downloaded from: http:///
ps026408-1208 port 0 zlf645 series flash mcus product specification 20 port 0 port 0 is an 8-bit bidirectional cmos-compatib le port. its eight i/o lines are configured under software control to create a nibble i/o port. the output drivers are push/pull or open-drain, controlled by bit 2 of the port configuration register . if one or both nibbles are required for i/o opera tion, they must be configured by writing to the port 0/1 mode register . after a hardware reset or a stop mode recovery, port 0 is configured as an input port. port 0, bit 7 is used as the transmit output of the uart wh en uart tx is enabled. the i/o function of port 0, bit 7 is overridde n by the uart serial output (txd) when uart tx is enabled (uctl[7] = 1). the pin must be configured as an output for txd data to reach the pin (p01m[6] = 0). an optional pull-up transistor is available as an user-selectable flash programming option on all port 0 bits with nibble select. figure 6 displays the port 0 configuration. figure 6. port 0 configuration zlf645 flash mcu port 0 (i/o) 44 open-drain i/o out in v dd pad resistive pull-up transistor flash programming option downloaded from: http:///
ps026408-1208 port 1 zlf645 series flash mcus product specification 21 port 1 port 1 is an 8-bit bidirectional cmos-compa tible i/o port. it can be configured under ? software control as inputs or outputs. a fl ash programming option bit is available to connect eight pull-up transistors on this port. bits programmed as output are globally programmed as either push/pull or open-drain. the power-on re set function resets with the eight bits of port 1 [p17: 10] configured as inputs. figure 7 displays the port 1 configuration. figure 7. port 1 configuration zlf645 flash mcu port 1 (i/o) 8 open-drain i/o out in v dd pad resistive pull-up transistor flash programming option downloaded from: http:///
ps026408-1208 port 2 zlf645 series flash mcus product specification 22 port 2 port 2 is an 8-bit bidirect ional cmos-compatible i/o port. its eight i/o lines can be independently configured under software control as inputs or outputs. port 2 is always available for i/o operation. a flash programm ing option bit is available to connect eight pull-up transistors on this port. bits progr ammed as outputs are globally programmed as either push/pull or open-drain. the power-on reset function resets with the eight bits of port 2 [p27:20] configured as inputs. port 2 also has an 8-bit inpu t or and and gate and edge detection circuitry, which can be used to recover from the stop mode. p20 can be programmed to access the edge-detec- tion circuitry in demodulation mode. figure 8 displays the port 2 configuration. figure 8. port 2 configuration zlf645 flash mcu port 2 (i/o) open-drain i/o out in v dd pad resistive pull-up transistor flash programming option downloaded from: http:///
ps026408-1208 port 3 zlf645 series flash mcus product specification 23 port 3 port 3 is an 8-bit cmos-compatible i/o port. port 3 consists of four fixed inputs ? (p33:p30), three fixed outputs (p37:p36:p35), and one multi-functioned pin (p34) that can function as an output only or as a bidire ctional open-drain i/o depending on whether the zlf645 mcu is in icp mode. p30, p31, p32, and p33 are standard cmos inputs with option enabled pull-up transistors and can be configured under software as in terrupts, as received data input to the uart block, as input to comparator circuits, or as input to the ir learning amplifier. p37, p36, and p35 are push/pull outputs and can be configured as outputs from ? counter/timers and/or comparator circuits. during the zlf645s por time, p34 is configured as an input pin with pull-up enabled. if after completing its por period, the zlf645 h as not detected this pin low and been put into icp mode, this pin will revert back to being a push/pull output only. for more details on the function of pin p34, see icp interface on page 53. downloaded from: http:///
ps026408-1208 port 3 zlf645 series flash mcus product specification 24 figure 9 displays the port 3 configuration. p31 can be used as an interrupt, analog comp arator input, infrared l earning amplifier input, normal digital input pin, and as a stop mode recovery source . when bit 2 of the port 3 mode register (p3m) is set, p31 is used as th e infrared learning amplifier, ir1. the refer- ence source for ir1 is gnd. the infrared learning amplifier is disabled during stop mode. when bit 1 of p3m is set, the part is in analog mode and the analog comparator, figure 9. port 3 configuration zlf645flash mcu downloaded from: http:///
ps026408-1208 port 3 zlf645 series flash mcus product specification 25 comp1 is used. the reference voltage for comp1 is p30 (p ref1 ). when in analog mode, p30 cannot be read as a digital input when the cpu reads bit 0 of the port 3 register; such reads always return a value of 1. also, when in analog mode, p31 cannot be us ed as a stop mode recovery source, as in stop mode the comparator is disabled and its output will not toggl e. the programming of bit 2 of the p3m register takes precedence over the programming of bit 1 in determining the function of p31. if both bits are set, p31 f unctions as an ir learning amplifier instead of an analog comparator. as displayed in figure 9 the output of the function selected for p31 can be used as a source for irq2 interrupt asse rtion. the irq2 interrupt can be configured based upon detecting a rising, falling, or edge-triggered input change using bits 6 and 7 of the irq register. the p31 output stage signal also goes to the counter/timer edge detec- tion circuitry in the same way that p20 does. p32 can be used as an interrupt, analog comparator, uart receiver, normal digital input and as stop mode recovery source. when bit 6 of uctl register is set, p32 functions as a receive input for the uart. when bit 1 of the p3m register is set, thereby placing port 3 into analog mode, p32 functions as an analog comparator, comp2. the reference voltage for comp2 is p33 (p ref2 ). p32 can be used as a rising, falling or edge-triggered interrupt, irq0, using irq re gister bits 6 and 7. if uart receiver interrupts are not enabled, the uart receive interrupt is used as the source of interrupts for irq0 instead of p32. when in analog mode p32 cannot be used as smr source because the compara- tors are turned off in stop mode. when in analog mode, p33 cannot be read by the cpu as a digital input through bit 3 of the port 3 register. in this case, a read of bit 3 of the port 3 register indicates whether stop mode recovery condition ex ists. reading a value of 0 indicates an smr condition; if the zlf645 mcu is in stop mode, it will ex it stop mode. reading a value of 1 indi- cates that no condition exists to ex it the zlf645 mcu from stop mode. additionally, when in analog mode, p33 cannot be used as an interrupt source. instead, the existence of a smr condition can generate an interrupt, if enabled. p33 can be used as a falling-edge interrupt, irq1, when not in analog mode. irq1 is also used as the uart t x interrupt and the uart brg interrupt. only one source is active at a time. if bit 7 and bit 5 of uctl are set to 1, irq1 will transmit an interrupt when the transmit shift register is empty. if bits 0 and 5 of uctl are set to 1 and bit 6 of uctl is cleared to 0, the brg interrupts will activate irq1. comparators and the ir am plifier are powered down by entering stop mode. ? for p30:p33 to be used as a stop mode recovery source during stop mode, these inputs must be placed into digital mode. when in analog mode, do not configure any port 3 input as a smr source. the configuration of these inputs must be re-initialized after stop mode recovery or por. note: downloaded from: http:///
ps026408-1208 port 3 zlf645 series flash mcus product specification 26 2 port 3 also provides output for each of the counter/timers an d and/or logic (see figure 10 ). control is performed by programming ctr1 bit 5 and bit 4, ctr0 bit 0, and ctr2 bit 0. table 12. summary of port 3 pin functions pin i/o in-circuit programmer counter/timers comparator interrupt iramp uart p30 in ref1 p31 in in an1 irq2 ir1 p32 in an2 irq0 uart rx p33 in ref2 irq1 p34 in/out icp t8 ao1 irout p35 out t16 p36 out t8/t16 p37 out ao2 downloaded from: http:///
ps026408-1208 port 3 zlf645 series flash mcus product specification 27 figure 10. port 3 counter/timer output configuration pcon, bit 0 p35 data t16_out p34 data t8_out ctr2, bit 0 ctr0, bit 0 p36 data t8/16_out p37 data com2 ctr1, bit 6 mux mux mux mux pad p35 pad p36 v pad p34 dd v dd v dd pcon, bit 0 mux pad p37 v dd p32 p33 p32 p3m d1 + p31 com1 i ref p30 p3m d1 p3m d2 + ir1 + mux icp v dd resistie pull-up transistor *see also in-circuit programmer chapter on p34 usage downloaded from: http:///
ps026408-1208 port 4 zlf645 series flash mcus product specification 28 comparator inputs in analog mode, p31 and p32 have a comparat or front end. the comparator reference is supplied by p33 and p ref1 . in analog mode, the p33 in ternal data latch and its corresponding irq1 are diverted to the stop mode recovery sources (excluding p31, p32, and p33) as displayed in figure 9 on page 24. in digital mode, p33 is used as bit 3 of the port 3 input register, which then generates irq1. comparators are powered down by entering stop mode. for p30:p33 to be used as an smr source, these inputs must be placed into digital mode. comparator outputs the comparators can be programmed to output on p34 and p37 by setting bit 0 of the pcon register. port 4 port 4 is an 8-bit bidirect ional cmos-compatible i/o port. its eight i/o lines can be independently configured under software control as inputs or outputs. port 4 is always available for i/o operation. a flash programm ing option bit is available to connect eight pull-up transistors on this port. bits progr ammed as outputs are globally programmed as either push/pull or open-drain. the por functi on resets with the eight bits of port 4 [p47:40] configured as inputs. figure 11 on page 29 displays the port 4 configuration. note: downloaded from: http:///
ps026408-1208 port 4 zlf645 series flash mcus product specification 29 figure 11. port 4 configuration zlf645 flash mcu port 4 (i/o) open-drain i/o out in v dd pad resistive pull-up transistor flash programming option downloaded from: http:///
ps026408-1208 port configuration register zlf645 series flash mcus product specification 30 port configuration register the port configuration register (see table 13 ) configures the port 0 output mode and the comparator output on port 3. the pcon register is located in expand ed register bank f, address 00h. pcon register is not reset after a stop mode recovery. also, for package types other than the 48-pin package, writes to bit 3 and bit 1 have no effect. table 13. port configuration register (pcon) bit 7 6 5 4 3 2 1 0 field reserved port 4 output mode port 0 output mode port 1 output mode comp/ir amp output port 3 reset x x x x 1 1 1 0 r/w w w w w address bank f: 00h; linear: f00h bit position value description [7:4] reserved must be written to 1; reads 11111b. [3] 01 port 4 output mode controls the output mode of port 4. open-drain push/pull [2] ? 01 port 0 output mode controls the output mode of port 0. write only; read returns 1. open-drain push/pull [1] ? 01 port 1 output mode controls the output mode of port 1. write only; read returns 1 open-drain push/pull [0] ? 01 comparator or ir amplifier output port 3 select digital outputs or comparator, and ir amplifier outputs on p34 and p37 . write only; read returns 1 . p34 and p37 outputs are digital. p34 is comparator 1 or ir amplifie r output, p37 is comparator 2 output. note: downloaded from: http:///
ps026408-1208 port 0/1 mode register zlf645 series flash mcus product specification 31 port 0/1 mode register the port 0/1 mode register (see table 14 ) determines the i/o direction of port 0 and ? port 1. the port 0 direction is nibble-progr ammable. bit 6 controls the upper nibble of port 0, bits [7:4]. bit 0 controls the lower nibb le of port 0, bits [3:0]. the port 1 direction is byte programmable. only p00, p01, and p07 are available for zlf645 flash mcu 20-pin configuration. table 14. port 0/1 mode register (p01m) bit 7 6 5 4 3 2 1 0 field reserved p07:p04 mode reserved port 1 mode reserved p03:p00 mode reset x1x x 1 x x1 r/w w w w address bank independent: f8h; linear: 0f8h bit position value description [7] 0 reserved must be written to 1. reads 1b. [6] 01 p07:p04 mode output input [5:4]* reserved must be written to 1. reads 1s. [3] * 01 port 1 mode output input [0] 01 p00:p03 mode output input * for package types other than the 48-pin package, writes to bit 3 have no effect. note: downloaded from: http:///
ps026408-1208 port 0 register zlf645 series flash mcus product specification 32 port 0 register the port 0 register (see table 15 ) allows read and write access to the port 0 pins. only p00, p01, and p07 are available for zlf645 flash mcu 20-pin configuration. table 15. port 0 register (p0) bit 7 6 5 4 3 2 1 0 field p07 p06 p05 p04 p03 p02 p01 p00 reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank 0C3: 00h; linear: 000h bit position r/w description [7] read 01 write 01 port 0 pin 7 available for i/o if uart tx is disabled. pin configured as input or output in p01m register. pin level is low. pin level is high. pin configured as output in p01m register, uctl[7]=0. assert pin low. assert pin high if configured as push-p ull; make pin high-impedance if it is ? open-drain. [6:0] read 01 write 01 port 0 pins 6C0 each bit provides access to the corresponding port 0 pin. pin configured as input or output in p01m register. pin level is low. pin level is high. pin configured as output in p01m register. assert pin low. assert pin high if configured as push-p ull; make pin high-impedance if it is ? open-drain. note: downloaded from: http:///
ps026408-1208 port 1 register zlf645 series flash mcus product specification 33 port 1 register the port 1 register (see table 16 ) allows read and write access to the port 1 pins. table 16. port 1 register (p1) bit 7 6 5 4 3 2 1 0 field p17 p16 p15 p14 p13 p12 p11 p10 reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank 0C3: 01h; linear: 001h note: for package types other than the 48-p in package, this register is ava ilable as a general-purpose register. bit position value description [7:0] read 01 write 01 port 1 pins 7C0 each bit provides access to the corresponding port 1 pin. pin configured as input or output in p01m register. pin level is low. pin level is high. pin configured as output in p01m register. assert pin low. assert pin high, if configured as push-pu ll; make pin high-impedance if it is open-drain. note: for packages other than 48-pin package, this regi ster is available as general-purpose register. downloaded from: http:///
ps026408-1208 port 2 mode register zlf645 series flash mcus product specification 34 port 2 mode register the port 2 mode register (see table 17 ) determines the i/o directio n of each bit on port 2. bit 0 of the port 3 mode register determin es whether the output drive is push/pull or ? open-drain. port 2 mode register is not reset after a stop mode recovery. table 17. port 2 mode register (p2m) bit 7 6 5 4 3 2 1 0 field p27 i/o definition p26 i/o definition p25 i/o definition p24 i/o definition p23 i/o definition p22 i/o definition p21 i/o definition p20 i/o definition reset 1 1 1 1 1 1 1 1 r/w wwwwwwww address bank independent: f6h; linear: 0f6h bit position value description [7] 0 1 defines p27 as output. defines p27 as input. [6] 0 1 defines p26 as output. defines p26 as input. [5] 0 1 defines p25 as output. defines p25 as input. [4] 0 1 defines p24 as output. defines p24 as input. [3] 0 1 defines p23 as output. defines p23 as input. [2] 0 1 defines p22 as output. defines p22 as input. [1] 0 1 defines p21 as output. defines p21 as input. [0] 0 1 defines p20 as output. defines p20 as input. note: downloaded from: http:///
ps026408-1208 port 2 register zlf645 series flash mcus product specification 35 port 2 register the port 2 register (see table 18 ) allows read and write access to the port 2 pins. table 18. port 2 register (p2) bit 7 6 5 4 3 2 1 0 field p 2 7p 2 6p 2 5p 2 4p 2 3p 2 2p 2 1p 2 0 reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank 0C3: 02h; linear: 002h bit position value description [7:0] read 01 write 01 port 2 pins 7C0 each bit provides access to the corresponding port 2 pin. pin configured as input or output in p2m register. pin level is low. pin level is high. pin configured as output in p2m register. assert pin low. assert pin high if configured as push-p ull; make pin high-impedance if it is open-drain. downloaded from: http:///
ps026408-1208 port 3 mode register zlf645 series flash mcus product specification 36 port 3 mode register the port 3 mode register (see table 19 ) is used to configure the functionality of port 3 inputs and the output mode of port 2. when b it 2 is set, the ir learning amplifier is used instead of the comp1 comparator, regardless of the value of bit 1. port 3 mode register is not reset after a stop mode recovery. table 19. port 3 mode register (p3m) bit 7 6 5 4 3 2 1 0 field reserved ir learning amplifier digital/analog mode port 2 open-drain reset xxxxx 0 0 0 r/w w w w address bank independent: f7h; linear: 0f7h bit position r/w value description [7:3] reserved must be written to 1. reads return 11111b. [2] ? w0 1 ir learning amplifier disabled. ir learning amplifier enabled with p31 configured as amplifier input. [1] ? w 01 digital/analog mode p30, p31, p32, p33 are digital inputs. p30, p32, and p33 are comparator inputs. if p3m[2]=0, p31 also function as a comparator input. if p3m[2]=1, p31 is the ir amplifier input. [0] ? w0 1 port 2 open-drain. port 2 push/pull. note: downloaded from: http:///
ps026408-1208 port 3 register zlf645 series flash mcus product specification 37 port 3 register the port 3 register (see table 20 ) allows read access to port pins p33 through p30 and write access to the port pins p37 through p34. table 20. port 3 register (p3) bit 7 6 5 4 3 2 1 0 field p37 p36 p35 p34 p33 p32 p31 p30 reset 0000xxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address banks 0C3: 03h; linear: 003h bit position value description [7] ? write 01 port 3, pin 7 output writes to this bit do not affect the pin state if write-only register bit pcon[0] is set to1, which configures p37 as the ? comparator 1 or ir amplifier output. p37 asserted low if pcon[0]=0. p37 asserted high if pcon[0]=0. a read returns the last value written to this bit. [6] write 01 port 3, pin 6 output writes to this bit do not affect the pin state if register bits ctr1[7:6]=01, which configures p36 as the timer 8 and timer 16 combined logic output. p36 asserted low. p36 asserted high. a read returns the last value written to this bit. [5] write 01 port 3, pin 5 output writes to this bit do not affect the pin state if register bit ctr2[0]=1, which configures p35 as the timer 16 output. p35 asserted low. p35 asserted high. a read returns the last value written to this bit. [4] write 01 port 3, pin 4 output writes to this bit do not affect the pin state if write only register bit pcon[0]=1 which configures p34 as a comparator 2 output, register bit ctr0[0]=1 which configures p34 as time r 8 output, or if the device is in icp mode as described in the icp interface on page 53. p34 asserted low. p34 asserted high. a read returns the last value written to this bit. downloaded from: http:///
ps026408-1208 port 3 register zlf645 series flash mcus product specification 38 port 3 register is not reset after a stop mode recovery. [3] read 01 0 1 port 3, pin 3 input writing this bit has no effect. if p3m[1]=0: p33 is low. p33 is high. if p3m[1]=1 or smr4[4]=1: smr condition exists. smr condition does not exist. [2] read 01 0 1 port 3, pin 2 input writing this bit has no effect. if p3m[1]=0: p32 input is low. p32 input is high. if p3m[1]=1: comparator 2 output is low. comparator 2 output is high. [1] ? read 01 0 1 0 1 port 3, pin 1 input writing this bit has no effect. if p3m[2:1]=00: p31 input is low. p31 input is high. if p3m[2:1]=01: comparator 1 output is low. comparator 1 output is high. if p3m[2:1]=10 or 11: ir amplifier ou tput is low. ir amplifier output is high. [0] read 01 1 port 3, pin 0 input writing this bit has no effect. if p3m[1]=0: p30 input is low. p30 input is high. if p3m[1]=1: reads as 1. bit position value description note: downloaded from: http:///
ps026408-1208 port 4 mode register zlf645 series flash mcus product specification 39 port 4 mode register the port 4 mode register (see table 21 ) determines the i/o directio n of each bit on port 4. bit 3 of the port configuration register (pco n) determines whether the output drive is push/pull or open-drain. port 4 mode register is not reset after a stop mode recovery. table 21. port 4 mode register (p4m) bit 7 6 5 4 3 2 1 0 field p47 i/o definition p46 i/o definition p45 i/o definition p44 i/o definition p43 i/o definition p42 i/o definition p41 i/o definition p40 i/o definition reset 11111111 r/w wwwwwwww address bank f: 09h; linear: f09h bit position value description [7] 0 1 defines p47 as output. defines p47 as input. [6] 0 1 defines p46 as output. defines p46 as input. [5] 0 1 defines p45 as output. defines p45 as input. [4] 0 1 defines p44 as output. defines p44 as input. [3] 0 1 defines p43 as output. defines p43 as input. [2] 0 1 defines p42 as output. defines p42 as input. [1] 0 1 defines p41 as output. defines p41 as input. [0] 0 1 defines p40 as output. defines p40 as input. note: downloaded from: http:///
ps026408-1208 port 4 register zlf645 series flash mcus product specification 40 port 4 register the port 4 register (see table 22 ) allows read and write access to the port 4 pins. table 22. port 4 register (p4) bit 7 6 5 4 3 2 1 0 field p 4 7p 4 6p 4 5p 4 4p 4 3p 4 2p 4 1p 4 0 reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address banks 0-3: 04h; linear: 004h bit position value description [7:0] read 01 write 01 port 4 pins 7C0 each bit provides access to the corresponding port 4 pin. pin configured as input or output in p4m register. pin level is low. pin level is high. pin configured as output in p4m register. assert pin low. assert pin high if configured as push-pu ll; make pin high-impedance if it is open-drain. downloaded from: http:///
ps026408-1208 memory and registers zlf645 series flash mcus product specification 41 memory and registers the z8 ? lxmc cpu used in the zlf645 series of flash mcus incorporates special ? features to extend the available memory space while maintaining the benefits of a z8 ? cpu core in battery-operated applications. flash program/constant memory the zlf645 series of flash mcus can address up to 64 kb of flash memory for object code (program instructions and immediate data ) and constant data (rom tables and data constants). the first 12 bytes of the memory are reserved for the six available 16-bit inter- rupt request (irq) vectors. on reset, program execution begins at address 000ch in the memory. execution rolls over to the beginnin g of the memory if the program counter address exceeds the flash memory size. the entire flash memory is available for either program code or constant data. outside of normal instruction fetches, the cpu can ac cess the flash memory by using ldc and ldci instructions. the ldc and ldci instru ctions use 16-bit addresses to access the memory. figure 12 displays the program/constant memory map for the device. figure 12. program/constant memory map program irq 0C5 or 000ch (reset) flash memory vectors 0000h = 16-bit address ( not to scale) constants up to 64 kb downloaded from: http:///
ps026408-1208 register file zlf645 series flash mcus product specification 42 register file the zlf645 series of flash mcus features up to 1024 bytes of register file space, ? organized in 256-byte banks. bank 0 contai ns 235 or 237 bytes of ram addressed as ? general purpose registers, 5 or 3 port addresses, and 16 control register addresses. for ? 20- or 28-pin packages, port 1 and port 4 registers of bank 0 are not implemented and there locations are available as general-purpos e registers. bank 1, bank 2, and bank 3; each contain 256 general-purpose register bytes. bank d and bank f; each contain 16 addresses for control registers. all other banks are reserved and must not be selected. the current bank is selected for 8-bit direct or indirect addressing by writing register pointer bits rp[3:0]. in the current bank, a 16-byte working register group (addressed as r0Cr15) is selected by writing rp[7:4]. a working register operand requires only 4 bits of program memory. there are 16 working register groups per bank (see figure 13 and figure 14 ). the 8-bit addresses in the range f0h C ffh (and the equivalent 4-bit addresses) are bank-independent, meaning they always access the control registers in bank 0, regardless of the rp[3:0] value. addresses in the range 00h C 03h always access the bank 0 port registers unless bank d or bank f is selected (port 01h is not implemented in this device). when bank d or bank f is selected, addresses 10hCefh access the bank 0 general- ? purpose registers. the ldx and ldxi instructions or indirect addressing is used to access the bank 1C3 ? registers not accessible by 8-bit or working register addresses (12-bit addresses100hC 103h, 1f0hC1ffh, 200hC203h, 2f0hC2ffh, 300hC303h, and 3f0hC3ffh). see linear memory addressing on page 45. stack the stack pointer register provides either 16 -bit or 8-bit of stack pointer addressability depending upon the programming of bit 3 of u ser option byte 1 (for more details, see flash option bits on page 171). 16-bit stack addressability when programmed for 16-bit stack addressab ility, the stack address is formed as a ? combination of the spl and sph registers locat ed at addresses ffh and feh. for 1k and ? 512 b ram products, the most significant 6 or 5 bits, respectively of the sph register are ignored. the stack address is mapped to a particular ram memory location by the ? following formula: bank = {2'b0, sph[1:0]} group = spl[7:4] register number = spl[3:0] with the zlf645 mcu configured for 16-bit st ack addressability, stack reads or writes to ? bank 3, 2, 1, or 0 group f registers or to any of the port re gisters actually accesses downloaded from: http:///
ps026408-1208 register file zlf645 series flash mcus product specification 43 shadow registers implemented within the ram memory. this enables the entire 1k or 512 b, depending on the product, of the ram memory to be used for the stack. 8-bit stack addressability for 8-bit stack addressability, only the spl regist er is used for stack addressing and stack operations that use the stack pointer always address bank 0, independent of the rp[3:0] setting. for more detail s on the stack, refer to z8 ? lxmc cpu core user manual (um0215) . when in 8-bit stack addressability mode, the bank 0 register feh can be used to store user data. see stack pointer register on page 48. figure 13. register file 8-bit banked address map cpu control f0h-ffh ports 00h-04h general purpose registers 05h-efh cpu control f0h-ffh ports 00h-04h general purpose registers 05h-efh cpu control f0h-ffh cpu control f0h-ffh cpu control f0h-ffh peripheral control 00h-0fh bank d general purpose registers 10h-efh cpu control f0h-ffh peripheral control 00h-0fh bank f general purpose registers 10h-efh bank d bank f = bank-independent address (always accesses bank 0) ** ** ** for 20 and 28 pin parts, the port01 and port04 locations become available for use as general purpose registers banks 1-3 bank 0 downloaded from: http:///
ps026408-1208 register file zlf645 series flash mcus product specification 44 figure 14. register pointerdetail 00 register group 2 register group 1 register group 0 i/o ports (banks 0-3 only) register group f ** * the upper nibble of the register file address provided by the register pointer specifies the active working group register r7 r6 r5 r4 r3 r2 r1 r0 specified working register group 0f 10 1f 20 2f 30 3f 40 4f d0 df e0 ef f0 ff r4 to r0* r15 to r5 r15 to r0 the lower nibble of the register file address provided by the instruction points to the specified register register pointer (rp), 0fdh active group active bank * rp=00: selects register bank 0, working register group 0 downloaded from: http:///
ps026408-1208 register file zlf645 series flash mcus product specification 45 register pointer example r253 rp = 00h r0 = port 0 r1 = port 1 r2 = port 2 r3 = port 3 r4 = port 4 but if: r253 rp = 0dh r0 = ctr0 r1 = ctr1 r2 = ctr2 r3 = ctr3 r4 = tc8l the counter/timers are mapped into erf grou p d. access is easily performed using the following code segment: ld rp, #0dh ; select erf d for access to bank d ; (working register group 0) ld r0,#xx ; load ctr0 ld 1, #xx ; load ctr1 ld r1, 2 ; ctr2 ?? ctr1 ld rp, #7dh ; select expanded register bank d and working ; register group 7 of bank 0 for access. ld 71h, 2 ; ctr2 ?? register 71h ld r1, 2 ; ctr2 ?? register 71h linear memory addressing in addition to using the rp register to designate a bank and working register group for ? 8-bit or 4-bit addressing, progra ms can use 12-bit linear addressing to load a register in any other bank to or from a register in the cu rrent bank. linear addressing is implemented through the ldx and ldxi instructions only. linear addressing treats th e register file as if all the registers are logically ordered en d-to-end, as opposed to being grouped into banks and working register groups, as displayed in figure 15 on page 47. for linear addressing, register file addresses are numbered sequentially from bank 0, register 00h to bank 0, register ffh, then continuing with bank 1, register 00h, and so on up to bank f, register ffh. using the ldx and/or the ldxi instructions, either the target or destination register location can be addressed through a 12-bit linear address value stored in a general-purpose register pair. downloaded from: http:///
ps026408-1208 register file zlf645 series flash mcus product specification 46 example for example, the following code uses linear addressing for the source of a register transfer operation and uses a working register address for the target: srp #%23 ;set working register group 2 in bank 3 ld r0, #%55 ;load 55 into working register r0 in the current ;group and bank (linear address 320h) srp #%12 ;set working register group 1 in bank 2 ld r6, #%03 ;load high byte of source linear address (0320h) ld r7, #%20 ;load low byte of source linear address (0320h) ld r0, @rr6 ;load linear address 320h contents (55h) into ;working register r0 in the current group and ;bank (linear address 210h) in the above code, the source register is re ferred through a linear address value contained within registers r6 and r7, whereas the destin ation is referenced via the srp setting and a working register. for more in formation about instructions on the usage of ldx and ldxi instructions, refer to z8 ? lxmc cpu core user manual (um0215) . the lde and ldei instructions that existed in the z8 cpu ar e no longer valid; they have been replaced by the ldx and ldxi instructions. note: downloaded from: http:///
ps026408-1208 register file zlf645 series flash mcus product specification 47 figure 15. register file ldx, ldxi linear 12-bit address map cpu control f0h-ffh ports 00h-04h general purpose registers 05h-efh general purpose registers 100h-3ffh peripheral control d00h-d0fh reserved d10h-dffh peripheral control f00h-f0fh bank d bank f ** ** ** for 20 and 28 pin parts, the port01 and port04 locations become available for use as general purpose registers reserved f10h-fffh bank 0 banks 1-3 downloaded from: http:///
ps026408-1208 register pointer register zlf645 series flash mcus product specification 48 register pointer register the upper nibble of the register pointer register (see table 23 ) selects which working ? register group is accessed. a working register gr oup consists of 16 bytes. the lower nibble selects the expanded register file bank; for zlf645 mcu, banks 0, 1, 2, 3, f, and d are implemented. a 0h in the lower nibble allows the normal register file (bank 0) to be addressed. any other value from 01h to 0fh exchanges the lower 16 registers to an expanded register bank. stack pointer register through a flash programmable option bit, th e stack pointer register of the zlf645 mcu is either one or two bytes providing either 8- bit or 16-bit of stack addressing. when not enabled through the option bit for 16-bit stack addressability, th e sph register can be used as a user data register (user). the stack pointer resides in the ram and when the zlf645 mcu is programmed for 8-bit addressing, this stack pointer resides in bank 0 of the ram only. with 16-bit a ddressing, the entire rams address space is available for use as the stack. the stack address is decremented prior to a push operation and incremented after a pop operation. the stack address always points to the data stored at the top of the stack (the lowest stack address). during a call instruction, the contents of the program counter are saved on the stack. interrupts cause the cont ents of the program counter and flags regis- ters to be saved on the stack. an overflow or underflow can occur when the stack address is incremented or decremented during normal operations. you must prevent this occur- rence or unpredictable operations may result (see table 24 on page 49). table 23. register pointer register (rp) bit 7 6 5 4 3 2 1 0 field working register group pointer register bank pointer reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: fdh; linear: 0fdh bit position value description [7:4] ? 0hCfh working register group pointer determines which 16-byte wo rking group is addressed. [3:0] ? 0hCfh register bank pointer determines which bank is active. downloaded from: http:///
ps026408-1208 stack pointer register zlf645 series flash mcus product specification 49 table 25. stack pointer register high byte (sph) or user data register (user) 1. for devices with 1k bytes of ram and w ith 16-bit stack pointer mode enabled, the upper 6 bits of this register are un used for stack addressi ng. for devices with 512 bytes of ram and with 16-bit stack pointer mode enabled, the upper 7 bits of this register are unused for stack addressing. 2. when zlf645 mcu is not in 16-bit stack pointer mode, this register is available to store use user data and its functi onality is identical to other maxim ? crimzon products such as the zlp12840 and zlr 64400 mcus. when available for user data, this register must not be used as a counter for the djnz instruction. table 24. stack pointer register low byte (spl) bit 7 6 5 4 3 2 1 0 field stack pointer reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: ffh; linear: 0ffh bit position value description [7:0] 00-ff stack pointer bit 7 6 5 4 3 2 1 0 field stack pointer reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: feh; linear: 0feh notes: downloaded from: http:///
19-4572; rev 0; 4/09 register file summary zlf645 series flash mcus product specification 50 register file summary table 26 lists each linear (12-bit) register file ad dress to the associated register, mnemonic, and reset value. the table also lists the register bank (or banks) and corresponding 8-bit address (if any) for each register and a page link to the detailed register table. throughout this document, an x denotes an undefined digit. a (dash) in a table cell indicates that the corresponding attribute does not apply to th e listed item. reset value dig- its (highlighted in grey) are not reset by a stop mode recovery. register bit smr[7] (shown in boldface ) is set to 1 instead of reset by a stop mode recovery. ? table 26. register file address summary address (hex) reset 12-bit bank 8-bit register description mnemonic page no 000 0C3 00 port 0 register p0 xxh 32 001 0C3 01 port 1 register p1 xxh 33 002 0C3 02 port 2 register p2 xxh 35 003 0C3 03 port 3 register p3 0xh 37 004 0C3 04 port 4 register p4 xxh 37 005C00f 0 05C0f general-purpose registers ? (bank 0 only) xxh 010C0ef 0,d,f 10Cef general-purpose registers ? (banks 0, d, f) xxh 0f0 all f0 reserved 0f1 all f1 uart receive/transmit data register urdata/ utdata xxh 95 0f2 all f2 uart status register ust 0000_0010b 95 0f3 all f3 uart control register uctl 00h 97 0f4 all f4 uart baud rate generator constant register bcnst ffh 98 0f5 all f5 reserved 0f6 all f6 port 2 mode register p2m ffh 34 0f7 all f7 port 3 mode register p3m x x x x _ x 0 0 0b 36 0f8 all f8 port 0/1 mode register p01m x1 xx_1 xx1 b 31 downloaded from: http:///
19-4572; rev 0; 4/09 register file summary zlf645 series flash mcus product specification 51 0f9 all f9 interrupt priority register ipr xxh 130 0fa all fa interrupt request register irq 00h 131 0fb all fb interrupt mask register imr 0 xxx_xxxxb 133 0fc all fc flags register flags xxh 160 0fd all fd register pointer register rp 00h 48 0fe all fe user data register/stack pointer register high byte 1 user/sph xxh 49 0ff all ff stack pointer register low byte spl xxh 49 100C103 general-purpose registers (12-bit only) xxh 104C1ef 1 04Cef general-purpose registers xxh 1f0C203 general-purpose registers (12-bit only) xxh 204C2ef 2 04Cef general-purpose registers xxh 2f0C303 general-purpose registers (12-bit only) xxh 304C3ef 3 04Cef general-purpose registers xxh 3f0C3ff general-purpose registers (12-bit only) xxh 400Ccff reserved d00 d 00 counter/timer 8 control register ctr0 000 0_ 0 0 00b 119 d01 d 01 timer 8 and timer 16 common functions register ctr1 00 0 0_0000b 121 d02 d 02 counter/timer 16 control register ctr2 000 0_ 0 000b 124 d03 d 03 timer 8/timer 16 control register ctr3 00 0 0_ 0 xxxb 126 d04 d 04 counter/timer 8 low hold register tc8l 00h 118 d05 d 05 counter/timer 8 high hold register tc8h 00h 117 d06 d 06 counter/timer 16 low hold register tc16l 00h 117 d07 d 07 counter/timer 16 high hold register tc16h 00h 116 d08 d 08 timer 16 capture low register lo16 00h 116 table 26. register file address summary (continued) address (hex) reset 12-bit bank 8-bit register description mnemonic page no downloaded from: http:///
19-4572; rev 0; 4/09 register file summary zlf645 series flash mcus product specification 52 d09 d 09 timer 16 capture high register hi16 00h 115 d0a d 0a timer 8 capture low register lo8 00h 115 d0b d 0b timer 8 capture high register hi8 00h 114 d0c d 0c low-voltage detection register lvd 1111_1000b 140 d0d reserv ed d0e d 0e user option byte 0 opt0 ffh 172 d0f d 0f user option byte 1 opt1 ffh 174 d10Cdff reserved (8-bit access goes to bank 0) f00 f 00 port configuration register pcon x x x x _ 1 1 1 0b 30 f01 f 01 flash control and flas h status register fctl/fstat 0 0 0 0_0 0 0 0b 76 / 77 f02 f 02 flash page select and sector protect register fps/fsec 0 0 0 0_0 0 0 0b 78 / 79 f03 f 03 flash frequency high byte register ffreqh 0 0 0 0_0 0 0 0b 80 f04 f 04 flash frequency low byte register ffreql 0 0 0 0_0 0 0 0b 80 f05Cf08 reserved f09 f 09 port 4 mode register p4m ffh 39 f0a f 0a stop mode recovery register 4 smr4 x x x 0 _ 0 0 0 0b 156 f0b f 0b stop mode recovery register smr 0 0 1 0_ 0 0 00 b 146 f0c f 0c stop mode recovery register 1 smr1 00h 150 f0d f 0d stop mode recovery register 2 smr2 x 0 x 0 _ 0 0 x xb 152 f0e f 0e stop mode recovery register 3 smr3 x0h 155 f0f f 0f watchdog timer mode register wdtmr 0 0 0 0 _ 1 1 0 1b 142 f10Cfff reserved (8-bit access goes to bank 0) 1 when zlf645 is programmed for 16-bit stack addressability, th e value in this register is used as the high byte of a ? 16-bit stack pointer. table 26. register file address summary (continued) address (hex) reset 12-bit bank 8-bit register description mnemonic page no downloaded from: http:///
19-4572; rev 0; 4/09 icp interface zlf645 series flash mcus product specification 53 icp interface the icp interface of the zlf645 is a single pin rs-232 like interface for performing programming, reads, and memory erasures to the zlf645s flash memory. for enabling the zlf645 into icp mode and for performi ng icp operations, the zlf645s p34 pin which normally functions as an output only is used. enabling icp mode as mentioned previously, the zlf645s gpio pin p34 is multi-functioned to be used for putting the zlf645 into icp mode and for icp communications once it is in that mode. entry into icp mode takes place during the zlf645s power on reset period. during the zlf645s power on reset period, the p34 pin which normally is an output only pin is ? configured by the zlf645 as an input with pu ll-up enabled. if during this time this pin is driven low and held low until the end of the power on reset period, the zlf645 will be put into icp mode. once in icp mode, the p34 pin operates as an open-drain output ? bidirectional pin with pull-up enabled. the power on reset period as can be seen from the electrical specs section of this document can have a duration range of between 2.5 ms and 10 ms. to ensure proper entry into icp mode, the p34 pin should be driven low and held low a minimum of 10 ms after power up. if during the zlf645s power on reset period, the p34 pin is never driven low, pin p34 will be pulled high through its pull-up device. in this case, if p34 remains high until the end of the power on reset period, the zlf645 will go into normal user mode and p34 will revert back to being an output pin only. to ensure proper entry into user mode when it is not intended to put the zlf645 into icp mo de, it is important that in the customer ? application p34 only be connected to capacitive load s. this is due to th e weak nature of its pull-up device, which can have a resistance ranging between 100 k ? up to 600 k ?? depending on voltage, temperature, and process. state of zlf645 in icp mode the operating characteristics of the device in icp mode are: the cpu stops executing instructions. all on-chip peripherals are disabled. the zlf645 constantly refreshes the watchdog timer, if enabled. the p34 pin is configured as a bidirectiona l pin with pull-up enabled and with the ? output stage configured as open-drain. the bidirectional control of the pins comes from the icp tx/rx logic. downloaded from: http:///
19-4572; rev 0; 4/09 enabling flash accesses through the icp zlf645 series flash mcus product specification 54 enabling flash accesses through the icp after the zlf645 is in icp mode, the flashctl bit of the icp control register must be programmed to 1 before flash accesses are enabled through the icp interface. icp interface logic architecture auto-baud system clock transmitter receiver icp pin flash controller z8 flash control detector/generator interface the icp logic within the zlf645 mcu consists of four prim ary functional blocks: trans- mitter, receiver, auto-baud detector/generator, and flash controller interface. figure 16 displays the architec ture of the icp. figure 16. in-circuit programmer block diagram icp interface operation after the zlf645 mcu is in icp mode, pin p 34 acts a bidirectiona l open-drain interface with internal pull-ups used for transmitting an d receiving the data. data transmission is half-duplex, in that transmit an d receive cannot occur simultaneously. serial data on p34 is sent using the standard asynchronous data fo rmat defined in rs-232. this pin creates an interface from the zlf645 mcu to the serial port of a host pc using minimal external hardware. figure 17 displays the recommended method of connecting p34 pin to an ? rs-232 connection using an open-drain buffer. the icp pin must always be connected to v dd through an external pull-up resistor. downloaded from: http:///
rs-232 tx rs-232 rx rs-232 transceiver v dd icp pin 10 k ? open-drain buffer 19-4572; rev 0; 4/09 icp interface operation zlf645 series flash mcus product specification 55 for operation of the icp, all power pins (v dd and av dd ) must be supplied with power and all ground pins (v ss and av ss ) must be properly grounded. figure 17. interfacing the in-circuit programming pin p34 with an rs-232 interface (2) icp data format s t a r td 0d 1d 2d 3d 4d 5d 6d 7s t o p the icp interface uses the asynchronous data format defined for rs-232. each character is transmitted as 1 start bit, 8 data bits (lea st significant bit first), and 1.5 stop bits ? (see figure 18 ). figure 18. icp data format icp auto-baud detector/generator to run over a range of baud rates (data bits per second) with various system clock frequencies, the icp contains an auto-baud de tector/generator. after a reset, the icp is non-active until it receives data. the icp requires that the first characte r sent from the host is character 80h . the character 80h has eight continuous bits low (one start bit plus 7 data bits), framed between high bits. the auto-baud detect or measures this period and sets the icp baud rate generator accordingly. the auto-baud detector/generator is cloc ked by the system clock. the minimum baud rate is the system clock frequency divided by 512. if the datastream can be synchronized with the system clock, the auto-baud generator can run as high as the system clock frequency divided by 2. caution: downloaded from: http:///
19-4572; rev 0; 4/09 icp interface operation zlf645 series flash mcus product specification 56 for optimal operation with asynchronous da tastreams, the maximum recommended baud rate is the system clock frequency divide d by 8. the maximum possible baud rate for asynchronous datastreams is the system clock fre quency divided by 4, but this theoretical maximum is possible only for low no ise designs with clean signals. table 27 lists minimum and recommended maximum baud rates for sample crystal frequencies. if the icp receives a serial break (nine or more continuou s bits low) the auto-baud detector/generator resets. y ou can reconfigure the auto-baud detector/generator by sending character 80h. icp serial errors the icp can detect any of the following erro r conditions on the p34 pin when in icp mode: serial break (a minimum of nine continuous bits low). framing error (received stop bit is low). transmit collision (icp and host simultaneou s transmission detected by the icp). when the icp detects one of these errors, it aborts any command currently in progress, transmits a four character long serial break back to the host, and resets the auto-baud detector/generator. a framing error or tr ansmit collision can be caused by the host sending a serial break to the icp. because of the open-drain nature of the interface, returning a serial break break b ack to the host only extends the length of the serial break, if the host releases the serial break early. the host transmits a serial break on the ic p pin when first connecting to the device or recovering from an error. a serial break from the host resets the auto-baud generator/ detector but does not resets the icp control register . a serial break leaves the device in debug mode if that is the current mode. the icp is held in reset until the end of the serial break when the icp pin returns high. be cause of the open-drain nature of the icp pin, the host can send a serial break to the icp even if the icp is transmitting a character. table 27. icp baud-rate limits system clock frequency ? (mhz) recommended maximum baud rate (kbps) recommended standard pc baud rate (bps) minimum baud rate (kbps) 8.0 1000.0 737280 15.6 1.0 125.0 115,200 1.95 0.032768 (32 khz) 4.096 2400 0.064 downloaded from: http:///
19-4572; rev 0; 4/09 icp in- circuit programming commands zlf645 series flash mcus product specification 57 as the icp interface uses a single pin for both receive and transmit, it can only receive or transmit at a given time. for the most part, th is is not a problem, as the icp uses a host driven protocol (z8 ? does not send any data without the host asking for it). to aid the icp in avoiding collisions, the tran smitter waits an additional 1/2 bit times after a stop bit is fully received or transmitted before it starts tran smission of a character. on the other hand, the receiver starts searching for a start bit as soon as the middle of the stop bit has been sampled and is valid. the transm itter does not start if another character is being received. icp in-circuit programming commands the host communicates to the icp by sending icp commands using the icp interface. during normal operation, only a subset of th e icp commands are available. in flash control mode, all icp commands are availa ble, but for few commands their access to the flash is qualified based upon the program ming of the flash read/write protect option bit ( flrwp ) or the lower half flash read/write protect option bit ( flprot1 ). when either of these bits is enabled, some of the icp commands will have reduced flash ? memory access or will be disabled completely. table 28 is a summary of the icp commands. each icp command is described in further detail in the bulleted list following this table. table 28 also indicates those commands that operate when the device is not in flash control mode (normal operation) and how those commands are effected by programming of the flrwp and flprot1 option bits. table 28. in-circuit programmer commands icp command command byte enabled when not in flash control mode? disabled by ? flash read/write protect option bits (flrwp and/or flprot1) read icp revision 00h yes reserved 01h read icp status register 02h yes reserved 03h no write icp control register 04h yes read icp control register 05h yes reserved 06h C 07h no write flash controller registers 08h no downloaded from: http:///
19-4572; rev 0; 4/09 icp in- circuit programming commands zlf645 series flash mcus product specification 58 in the following bulleted list of icp commands, data and comm ands sent from the host to the icp are identified by icp ? command/data . data sent from the icp back to the host is identified by icp ? data : read icp revision (00h) the read icp revision command determines the version of the icp. if icp commands are added, re moved, or changed, the revision number changes. icp ? 00h ? icp ? icprev[15:8] (major revision number) ? icp ? icprev[7:0] (minor revision number) read flash controller registers 09h no write flash memory 0ah no if flrwp en abled, comm and is disabled for en tire flash main memory an d p age 3 of the information ar ea. if flprot1 enabled, co mmand disab led for page 3 of the in formation are a and lower ha lf of ma in me mory only. read flash memory 0bh no if flrwp en abled, comm and is disabled fo r t he f lash m ain memory. if flprot1 ena bled, command disabled for the lower half of main memory only. reserved 0ch C 0dh disabled read program memory crc 0eh no reserved 0fh C1ah read icp autobaud register 1bh yes reserved 1ch C efh write test mode register f0h yes read test mode register f1h yes reserved f2h C ffh table 28. in-circuit programmer commands (continued) icp command command byte enabled when not in flash control mode? disabled by ? flash read/write protect option bits (flrwp and/or flprot1) downloaded from: http:///
19-4572; rev 0; 4/09 icp in- circuit programming commands zlf645 series flash mcus product specification 59 this command when executed returns a value of 0132h which is the revision id assigned for the zlf645 mcu. read icp status register (02h) the read icp status register command reads the icpstat register. icp ? 02h ? icp ? icpstat[7:0] write icp control register (04h) the write icp control register command writes the data that follows the co mmand to the icpctl register. icp ? 04h ? icp ? icpctl[7:0] read icp control register (05h) the read icp control register command reads the value of the icpctl register. icp ? 05h ? icp ? icpctl[7:0] write flash controller registers (08h) the write flash controller register ? command allows writes to the flash controlle r registers. this command configures the flash controller for flash memory accesses through the write flash memory and read flash memory commands. if the device is not in flash control mode, the register address and data values are discarded. icp ? 08h ? icp ? register address[15:0] ("0fh" for all flash ctrl regs) ? icp ? register address[7:0] ? icp ? size[7:0] ? icp ? 1-256 data bytes read flash controller registers (09h) the read flash controller command al- lows reads of the flash controller registers. if the device is not in flash control mode this command returns ffh for all the register values. icp ? 09h ? icp ? register address[15:0] ("0fh" for all flash ctrl regs) ? icp ? register address[7:0] ? icp ? size[7:0] ? icp ? 1-256 data bytes write flash memory (0ah) the write flash memory comm and is used to write data to the main memory area or information area of the flash memory. the command has equivalent functionality to the cpu writin g the memory through the ldc and ldci instructions. data can be written 1 to memsize bytes at a time where memsize repre- sents the size (32 kb or 64 kb) of the flash memory for the product option chosen (the memsize number of bytes can be written by se tting the size to 0). should a size value greater than the maximum memory size be given by the user, the actual size value downloaded from: http:///
19-4572; rev 0; 4/09 icp in- circuit programming commands zlf645 series flash mcus product specification 60 for the command will default to the ma ximum memory size. the on-chip flash ? controller must be written to and unlocked for the programming operation to occur. ? if the flash controller is not unlocked, the data is discarded. also, data is discarded for writes to protected areas of the flashs main or information page 3 areas based upon the settings of the read/wr ite protect option bits in user option byte 1 (opt1) register. icp ? 0ah ? icp ? flash memory address[15:8] ? icp ? flash memory address[7:0] ? icp ? size[15:8] ? icp ? size[7:0] ? icp ? 1-memsize data bytes read flash memory (0bh) the read flash memory command is used to read data from the flashs main memory area or info rmation area. this command is equivalent to the cpu reading the memory through the ldc and ldci instructions. data can be read 1 to memsize bytes at a time where memsize represents the size (32 kb or ? 64 kb) of the flash memory for the product option chosen (the memsize number of bytes can be written by setting the size to 0) . depending on the settings of the read/write protect option bits in user option byte 1 register, reads to protected areas of the flashs main memory area will return ffh for the data. icp ? 0bh ? icp ? flash memory address[15:8] ? icp ? flash memory address[7:0] ? icp ? size[15:8] ? icp ? size[7:0] ? icp ? 1-65536 data bytes read flash main memory crc (0eh) the read flash main memory crc ? command computes and returns the cyclic redundancy check ( crc) of the flashs main memory using the 16-bit crc-ccitt pol ynomial. if the device is not in icp mode, this command returns ffffh for the crc value. unlike most other icp read commands, there is a delay from issuing of the command until the icp returns the data. the icp reads the main memory, calculates th e crc value, and returns the result. the delay is a function of the flash main memory size and is approximately equal to the system clock period multiplied by the numb er of bytes in the flash main memory. icp ? 0eh ? icp ? crc[15:8] ? icp ? crc[7:0] read icp autobaud register (1bh) the read icp autobaud register command reads the 12-bit icp autobaud valu e set during autobaud detection. icp ? 1bh icp ? (4b0000, autobaud[11:8]) downloaded from: http:///
19-4572; rev 0; 4/09 flash progra mming through the icp interface zlf645 series flash mcus product specification 61 icp ? autobaud[7:0] write test mode register (f0h) the write test mode register command writes the data that follows the command to the test mode register (testmode). icp ? f0h icp ? testmode[7:0] read test mode register (f1h) the read test mode register command reads the value of the testmode register. icp ? f1h icp ? testmode[7:0] icp ? autobaud[7:0] flash programming through the icp interface differences between cpu based a nd icp based flash programming/ erase access following are the differences for the allowed access capabilities be tween flash accesses initiated by the cpu through instruction code and tho se initiated through the icp ? interface: 1. the settings of the flash controllers sect or protect register (spr) are ignored for flash programming or page erase opera tions initiated through the icp interface. 2. mass erase operations can be executed through the icp interface. using icp commands for flash programming/read operations as described in the icp in-c ircuit programming commands, th ere are two commands that can be used for flash progr amming and flash data read operations. these commands are the write flash memory (0ah) and read flash memory (0bh) commands. to minimize the programming time re quired to program the flash memo ry using the icp interface the following considerations concer ning the use of these commands should be kept in mind: the write flash memory command can be used in two different ways for transmitting flash programming data. when 1 or more data bytes are to be programmed to one or more non-sequential flash memory address locations, a value of 0001h for the ? size [15:8] and size [7:0] arguments must be used. using the comm and in this way re- quires that, for each byte of data to be pr ogrammed, 6 bytes be transmitted across the icp. following is an example of the icp transmit sequence using the command, for programming two bytes of data: downloaded from: http:///
19-4572; rev 0; 4/09 flash progra mming through the icp interface zlf645 series flash mcus product specification 62 icp ? 0ah ? icp ? flash memory address1[15:8] ? icp ? flash memory address1[7:0] ? icp ? 00h ? icp ? 01h ? icp ? byte1[7:0] icp ? 0ah ? icp ? flash memory address2[15:8] ? icp ? flash memory address2[7:0] ? icp ? 00h ? icp ? 01h ? icp ? byte2[7:0] if multiple bytes are to be programmed into sequential address locations in the flash memory, the write flash memory command can be used so th at each byte of data to be programmed only 1 byte be transmitted across the icp, after the initial execution of the command. this is done simply by ex ecuting the command with a size value other than 0001h and providing the starting address of the flash memory area to be programmed. following is an example of the icp transmit sequence using the command, for programming 3 bytes of data to three sequential address locations of the flash memory: icp ? 0ah ? icp ? starting flash memory address[15:8] ? icp ? starting flash memory address[7:0] ? icp ? 00h ? icp ? 03h ? icp ? byte1[7:0] ? icp ? byte2[7:0] ? icp ? byte3[7:0] when using the write flash memory command to program bytes of data into the flash memory, there is no buffering of the data th at takes place between the icp interface and the flash memory. as a result the maximum rate at which data is programmed into the flash memory through the icp interface is dependent up on how long it takes the zlf645 to complete a flash memory byte programming op eration, once it is initiated by the icp. for the zlf645, the total progra mming time required to program one byte of data is approximately 65 s. when the write flash memory command is used to program multiple bytes of data to sequentia l address locations in the flash, then the maximum baud rate for flash programming through the icp is calculated as follows: if multiple non-sequential locations of the flash memory are to be programmed, the write flash memory command can be still be used. howe ver, as previously explained, each byte to be programmed requires 6 byt es be transmitted on the icp interface. to keep the icp interface data rate from lim iting how quickly multiple bytes can be ? max programming baud rate 1 icp byte 10 icp bits/byte ? 65 s/byte ? 153.8 kbaud == downloaded from: http:///
19-4572; rev 0; 4/09 flash progra mming through the icp interface zlf645 series flash mcus product specification 63 programmed in this case a higher baud rate can be used. considering the zlf645s sys- tem clock is of high frequency to support hi gher icp baud rates. the baud rate neces- sary to support maximum programming efficiency is calculated as follows: the read flash memory command can be used in the same two ways as described above for the write flash memory command. when using th e command to read mul- tiple bytes of data from sequential address locations within the flash memory, every byte read requires only 1 byte be received across the icp interface . as described for the write flash memory , there is no buffering of data that takes place between the icp interface and the flash memory during memory reads. this means, as described for the write flash memory command, the maximum baud rate that memory read operations can occur at is dependent upon how quickly the zlf645 completes a flash memory read operation, once it is initiated by the icp. a zlf645 memory read operation ? requires two system clock cycles to co mplete. considering a zlf645 system clock ? period of 250 ns, the theoretical maximu m baud rate reduces to the maximum baud rate supported by the devices system clock frequency, which is calculated as follows: the icp baud rate for read operations is significantly higher than for programming ? operations. max baud rate 6 icp byte 10 icp bits/byte ? 65 s/byte ? 922.8 kbaud == max baud rate 1 500 ns bit ? ?? ? 2 mbaud == downloaded from: http:///
19-4572; rev 0; 4/09 in-circuit prog ramming control register definitions zlf645 series flash mcus product specification 64 in-circuit programming cont rol register definitions icp control register the icp control register (see table 29 ) controls the state of the icp interface. this regis- ter is used to enter or exit flash control mode. table 29. icp control register (icpctl) bits 7 6 5 4 3 2 1 0 field flashctl reserved reset 0 0 000000 r/w r / wrr / wrrrrr bit position value description flashctl [7] ? 01 flash control mode when this bit is programmed to 1, the device enters flash control mode. when programmed to 1, this bit enables the icp to perform flash memory accesses through the devices flash controller. the device is operating in normal mode. the device is in flash control mode. [6:0] reserved must be written to 1. downloaded from: http:///
19-4572; rev 0; 4/09 in-circuit prog ramming control register definitions zlf645 series flash mcus product specification 65 icp status register the icp status register (see table 30 ) reports status information about the current state of the icp and the device. table 30. icp status register (icpstat) bits 7 6 5 4 3 2 1 0 field flashctl flprot1 flrwp reserved flwait reserved reset 0 0000000 r/w rrrrrrrr bit position value description [7] ? 01 flashctl when read, this bit indicates whether the device is in flash control mode. the device is operating in normal mode. the device is in flash control mode. [6] 0 1 flprot1 when read, this bit indicates the value of the devices flprot1 option bit as read from the user option byte 1 shadow register (opt1sr) on page 175. flprot1 mode is enabled. flprot1 mode is disabled. [5] 01 flrwp when read, this bit indicates the value of the devices flrwp option bit as read from the user option byte 1 shadow register. flrwp mode is enabled. flrwp mode is disabled. [4] reserved must be written to 1. [3] 01 flwait when read, this bit indicates whether an icp initiated flash program, page erase, or mass eras e operation is completed or not. an initiated flash programming, page eras e, or mass erase operation is now complete. a flash programming, page erase, or mass erase operation is still in progress and has not yet completed. no new flash operations must be started until this bit reads as a 0. [2:0] reserved must be written to 1. downloaded from: http:///
19-4572; rev 0; 4/09 exiting icp mode zlf645 series flash mcus product specification 66 test mode register the test mode register is used to enab le various device test or flash memory access modes. at present this regist er only provides configuration for a single mode where, once programmed, flash memory accesses bypass the devices flash controller and are done through the devices i/o pins. a complete descriptio n of this mode is available in the flash byte programming interface section. this regist er can only be read or written using the icp read/write test mode register commands. exiting icp mode the zlf645 mcu is taken out of icp mode under any of the following conditions: initiating a por with p36 held high du ring the entire reset period. lowering v dd until the zlf645 mcu reaches a vo ltage brownout reset state. table 31. test mode register (testmode) bits 7 6 5 4 3 2 1 0 field reserved f lash controller bypass mode reserved reset 00000 0 0 0 r/w r/w r r r r r/w r r bit position value description [7:3] reserved must be written to 1. reads return 0. [2] 0 1 flash controller bypass mode the device is not in flash controller bypass mode. the device is in flash controller bypass mode. [1:0] reserved must be written to 1. reads return 0. downloaded from: http:///
19-4572; rev 0; 4/09 flash controller zlf645 series flash mcus product specification 67 flash controllerflash memory overview the zlf645 products feature either 32 kb or 64 kb of non-volatile flash memory with read/write/erase capability. the flash memory provides a 16-bit data interface but ? supports both 16-bit and 8-bit programming and read operations. the flash memory can be programmed, read, or erased by the flas h controller directed by either the cpu through user code or through the in-circuit programmer (icp) interface pin with the zlf645 in icp mode. all user code or icp flash accesses use the flashs byte access mode where programs and reads occur 8 bits at a time. a flash byte programming inter- face, as described in the section flash byte programming interface on page 82, is also available for flash accesses through the devi ces gpio pins and bypassing the flash ? controller. when the flash byte programmi ng interface is used, flash programming and reads can be done either 8-bits or 16-bits at a time, depending on the package type of the device. the flash memory consists of two blocks, the main memory and the information block . the flash main memory is arranged in pages with 512 bytes per page. flash era- sures are not allowed on a byte/word basis and a 512-byte page is the minimum flash block size that can be erased. each page is divided into 8 rows of 64 bytes. the term page in the cont ext of the flash controller is not equivalent to the z8 ? lxmc cpu architectures program memory page. for flash contents protection, the flash main memory is also divided into sectors, ea ch sector containing 16 consecutive pages. in addition to the flash main memory, there is a 256-byte information block, arranged as 4 rows of 64 bytes. each row is defined as a page. user access is only allowed to page 3, where user definable option bits reside. pages 2-0 are for maxim ? internal use. information block does not have a flas h contents sector protection mechanism. table 32 lists the flash main memory configura tion for each device in the family of zlf645 products. the size and conf iguration of the information block is the same for all devices. figure 19 displays the flash memory arrangement. table 32. zlf645 products flash memory configurations part number flash size kbytes flash pages program memory addresses flash sector size zlf645xxxxx32 32 kb 64 0000hC7fffh 8 kb zlf645xxxxx64 64 kb 128 0000hCffffh 8 kb note: note: downloaded from: http:///
up to 64 kb flash main program memory 0000 up to 8 sectors 16 512-byte pages 1fff 2000 ffff addresses (hex) 3fff 4000 5fff 6000 7fff 8000 9fff a000 bfff dfff e000 256 b flash information memory 0000 4 pages addresses (hex) 00ff 00bf 00c0 007f for maxim 0080 003f 0400 sector 7sector 6 sector 5 sector 4 sector 3 sector 2 sector 1 sector 0 page 0 page 1 page 2 page 3 per sector 64 bytes each internal use c000 19-4572; rev 0; 4/09 flash memory overview zlf645 series flash mcus product specification 68 figure 19. flash memory arrangement flash information block the flash information block of flash memory is divided into two sections. page 3 of the information block is accessible by you or flash programmer vendor for programming, reading, or erasure through the zlf645s icp interface or its flash byte programming interface only, as desc ribed in the section flash byte programming interface on page 82. the cpu has no access to this area of memo ry. user option bytes 0 and 1 use addresses 00fe and 00ff respectively of the page 3 area and contain programmable bits with ? pre-defined functions. the flash read/write protect bits in user op tion byte 1 control the level of page 3 access allowed to you along with the users level of access to the flashs main memory. bytes 00c0 through 00fd of page 3 have no pre-defined f unction and are available to you for other operations. downloaded from: http:///
19-4572; rev 0; 4/09 flash controller overview zlf645 series flash mcus product specification 69 pages 0 through 2 (addresses 0000 through 00bf ), of the information area are reserved for maxim ? internal use and are inaccessible by yo u or programmer vend or, either through the icp interface or by using the flash byte programming interface. flash controller overview the flash controller provides the appropriat e flash controls and timing for byte/word ? programming, page erase, mass erase, a nd reading of the flash memory for flash accesses made by either the cpu or through th e icp interface. it also limits programming, erase, and read access to the flash memory based upon certain register and/or option bit settings. external acce sses through the zlf645s icp or flash byte programming inter- faces are limited by the flash controller based upon the programming of the zlf645s flash read/write protect bits in user optio n byte 1. accesses by the cpu during code exe- cution is limited based upon the programmi ng of the flash controllers sector protect (fsec) registers. all flash memory accesses through the flash cont roller are prevented unless the flash controller is in unlocked state. executing flash memory access es through the fl ash controller flash access timing control programming requirements before a program or erase operation can be executed by the flash controller on the flash memory, you must first configure the flash c ontrollers flash frequency high and low byte registers. these registers combine to form a 16-bit value ( ffreq ) that is used by the flash controller to control timing for flash pr ogram and erase operations. for proper tim- ing, the 16-bit binary flash frequency value must be programmed with the system clock frequency (in khz). this 16-bit binary flash frequency value is calculated using the following equation: using a 16-bit value ffreq value, the flash co ntroller is able to provide correct program and erase operation timing across a cpu cl ock frequency range of 1 mhz to 8 mhz. the system clock frequency depends on the flash memory programming of bit 2 of the user option byte 1 and on the register programming of bit 0 of the smr register and can be equal to the clock input frequency on the xtal1 pin, a divide by 2 of that input, a divide by 16 of that input, or a divide by 32 of that input. flash programming and erasure are not supported for cpu clock frequencies below 1 mhz or above 8 mhz. the flash frequency high and low byte registers must be loaded with the correct values. ffreq[15:0] system clock frequency (hz) 1000 ------------------------------------------------------------------------------- = caution: downloaded from: http:///
19-4572; rev 0; 4/09 flash controller overview zlf645 series flash mcus product specification 70 enabling the flash controller for flash memory accesses upon zlf645 reset, the flash controller is put into a locked state where flash accesses through the controller are disabled. before any flash memory accesses can take place through the flash controller it must be unlocke d. this functionality is designed to help protect against accidental programming or er asure of the flash memory by flash accesses initiated by the icp interface or by the cpu du ring code execution. to unlock the flash controller the icp or cpu must perform the following sequence of flash controller ? register write operations: 1. program the flash controllers page select (pgs) register with the page to be programmed or erased. 2. program the flash controllers flash cont rol register (fctl) with a value of 73h . 3. program the flash controllers flash cont rol register (fctl) with a value of 8ch . 4. program the flash controllers page select (pgs) register with the same value as programmed in step 1 above. failure to follow the exact register program ming sequence as described above causes the flash controller to revert back to locked st ate and the sequence must be repeated starting from step 1. for instance, if the two page se lect register writes in steps 1 and 4 do not match, the controller reverts to locked state. after unlocking the flash controller, a prog ramming or page erase operation can now be initiated through the flash controller to the pa ge pointed to by the page select (pgs) ? register. for example, once the flash controller is unlocked, writing a 95h to the flash control (fctl) register initiates a page er ase. for a description of how to execute ? programming, see byte programming on page 74. as mentioned in the flash memory overview on page 67, cpu initiated programming or erase operations may be limited by the fl ash controller base d upon the values ? programmed in the flash controllers sector protect (fsec) regist er. for cpu initiated operations, the operation must be to a non-protected sector for the flash controller to exe- cute the operation. for icp initiated programmin g or erase operations, or if the page to be programmed/erased is in the flash informati on area, the operation is executed indepen- dent of the sector protect (fsec) register settings. after unlocking a specific page, the icp or cpu can program any byte on that page or erase that page. for programmi ng, after a byte is written the page remains unlocked, allowing for subsequent writes to other bytes on the same page. once unlocked, the flash controller will revert to locked state under the fo llowing conditions: 1. the flash controller has completed any programming operations in progress and the icp or cpu writes the flash control (fctl) register with a value other than 95h or 63h . 2. the flash controller has successfully comple ted a page erase or mass erase operation. downloaded from: http:///
19-4572; rev 0; 4/09 flash controller overview zlf645 series flash mcus product specification 71 3. the cpu writes to the page select (pgs) register. figure 20 displays the basic flash controller ope ration considering code based cpu flash accesses and based upon the programming of th e flash controllers flash control (fctl), sector protect (fsec), and page select (fps) registers. as mentioned previously for icp based flash accesses, the only modification to figure 20 is that the programming of the sector protect (fsec) register is ignored and the icp has programming and erase access to a page independent of whether it resides in a protected sector. figure 20 does not ? display the effects of the flash read/write protect bits of user option byte 1. if either of these bits is enab led, their function takes priority over the operation description displayed in figure 20 in terms of when a page erase or byte programming access is allowed (for more details, see flash code protection against external access on page 73). downloaded from: http:///
reset page 73h no yes 8ch no yes program/erase enabled 95h or 63h no yes write fctl lock state 0 lock state 1 write fctl write fctl byte program erase write page select register write page select register page in no no unlocked protected sector? writes to page select register in lock state 1 result in a return to lock state 0 page select yes values match? yes 19-4572; rev 0; 4/09 flash controller overview zlf645 series flash mcus product specification 72 figure 20. flash controller operation flow chart downloaded from: http:///
19-4572; rev 0; 4/09 flash controller overview zlf645 series flash mcus product specification 73 flash code protection ag ainst external access the flash controller li mits flash access capabilities of the icp and flash byte program- ming interfaces based upon the flash read/write protect bits in user option byte 1. by programming these bits, you can configure the fl ash controller to block page 3 informa- tion area erasures, main memory reads, and main memory page erasures and programming as initiated through the icp or byte programming interfaces of the zlf645. for more information, see table 85 on page 174. flash code protection against accidental program and erasure as mentioned previously, the zlf645 products provide several levels of protection against accidental program and erasure of the flash main memory contents by icp and cpu accesses through the flash controller. through the flash controllers register locking mechanism, page select redundancy, and sector level pr otection control, the zlf645 products prov ide protection against accidental program and erasure of the flash main memory contents by cpu and icp accesse s, except that for the icp sector level protection is ignored. similar levels of protection are in place for the flash information area, minus the sector level protection. sector based flash protection for cpu initiated flash main memory accesses, programming/erase prot ection is possible on a sector level basis through programming of the flash controllers sector protect (fsec) register. for all zlf645 products, each sector contains 16 pages (of 512 bytes each). the sector protect (fsec) register controls the protection state of each flash sector. this register is address-shared with the page sel ect register. it can only be accessed with the flash controller in locked state. with the fl ash controller in locke d state, writing the flash control (fctl) register with a value 5eh enables the flash controllers sector protect register to be writte n. the next write performed to bank f, register address 02h then targets the flash controller s sector protect (fsec) register. the sector protect register is initialized to 0 on reset, putting each sector into an ? unprotected state. when a bit in the sect or protect register is written to 1, the corresponding sector within the flash memory ca n no longer be progra mmed or erased if for operations initiated by th e cpu. operations through the icp are unaffected by the part number numb er of sectors zlf645xxxxx32 4 zlf645xxxxx64 8 downloaded from: http:///
19-4572; rev 0; 4/09 flash controller overview zlf645 series flash mcus product specification 74 settings of the sector protect (fsec) register. after a bit of the sector protect register has been set, it cannot be cleared ex cept by powering down the device. byte programming all flash accesses either thr ough cpu code execution or through the icp interface occur using the flash memory byte mode of ope ration. the flash controller allows cpu programming access to the flashs main memo ry area only whereas the icp has access to both the main memory and the page 3 information area for programming. the flash memory is enabled for byte programming by e ither the cpu or the icp after unlocking the flash controller and executing either a mass erase or page erase operation. when the flash controller is unlocked and a main memo ry mass erase is executed, all flash main memory locations are available for byte progr amming by the cpu. in contrast, when the flash controller is unlocked and a main me mroy page erase is executed, only the locations of the selected page as per the page select (pgs) register are available for byte programming by the cpu. an erased flash byte contains all 1s ( ffh ). the programming operation can only be used to change bits from 1 to 0. to change a flash bit (or multiple bits) from 0 to 1 requ ires an erase operation through execution of either a page erase or mass era se command to the flash controller. byte programming can be accomplished through the icp by using the write memory command or by the z8 lxmc cpu through exec ution of the ldc or ldci instructions. for a description of the ldc and ldci instructions, refer to z8 ? lxmc cpu user ? manual (um0215) . during execution of a cpu initia ted programming operation the ? system clock to the cpu is halted preventing further code execution, however the system clock and the on-chip peripherals continue to operate. once the prog ramming operation is complete, the cpu resumes c ode execution. to exit programming mode and lock the flash the cpu can perform a write of any va lue to the flash control (fctl) register, except the mass erase or page erase commands. page erase the flash main memory can be erased one page (512 bytes) at a time. page erasing the flash memory sets all bytes in that page to the value ffh . the flash page select (pgs) register identifies the page to be erased. for cpu initiated page erase operations, only a page residing in an unprotected sector can be erased. with the flash controller unlocked and the active page set, writing the value 95h to the flash control (fctl) register initi- ates the page erase operation. as with programming, during execution of a cpu initiated page erase operation the system clock to th e cpu is halted preventing further code execu- tion, however the system clock and the on-chip peripherals continue to operate. once the page erase operation is complete, the cpu resumes code execution. if a page erase operation to the flashs main memory is performed using the icp, bit 3 of the icp status register can be polled to determine when the operation is complete. when the page erase is complete, th e flash controller returns to its locked state. although the downloaded from: http:///
19-4572; rev 0; 4/09 flash control register definitions zlf645 series flash mcus product specification 75 flash controller prevents cpu accesses to the flashs information block, the icp can ini- tiate a page erase to page 3 of information area by a similar process as used for the main memory. the only difference is that the icp mu st first write bit 7 of the flash page select (pgs) register to a 1 before writing the page erase command to the flash control (fctl) register. for more details, see table 34 on page 77. mass erase the flash main memory can also be mass erased using the flash controller, but only through the icp interface and not by the cpu. mass erasing the flash memory sets all bytes to the value ffh . with the flash controller unlocked, writing the value 63h to the flash control register initiates the mass erase operation. if a mass erase operation is performed using the icp, bit 3 of the icp stat us register is polled to determine when the operation is complete. when the mass erase is complete, the flash controller returns to its locked state. you cannot mass erase the information area. if either of the flash memory protect option bits are set as defined in the flash op- tion bits section, a mass erase of the flash' s main memory must be performed before page 3 of the flash's information area ca n be erased. these two operations must be done when the device is at operating voltage. that is, if a mass erase is followed with a power-down then power-up sequence, performing an information area page 3 erase will not erase its contents. flash control regi ster definitions flash control register the flash controller must be unlocked using the flash control (fctl) register (see table 33 ) before the flash controller is enab led for programming or erasing the flash memory. writing values of 73h and then 8ch sequentially to the fl ash control register unlocks the flash controller, as long as the other conditions described in enabling the flash controller for flash memory accesses on page 70 have been met. when the flash controller is unlocked, a mass erase initiate d by the icp, or page erase initiated by the icp or cpu can be executed by the flash c ontroller by writing th e appropriate command value to this register. execution of a page eras e applies only to the ac tive page selected in flash page select (fps) register. writing an invalid value or an invalid sequence returns the flash controller to its locked state. th e write-only flash control register shares its register file address with the read-only flash status register. caution: downloaded from: http:///
19-4572; rev 0; 4/09 flash control register definitions zlf645 series flash mcus product specification 76 table 33. flash control register (fctl) bits 7 6 5 4 3 2 1 0 field fcmd reset 00000000 r/w wwwwwwww address bank f, register address: 01h bit position value description [7:0] 73h 8ch 95h 63h 5eh fcmd flash command first unlock command. ? second unlock command. page erase command (from flash controller locked state, must be the third command written to this register to initiate page erase). mass erase command (ignored by flash controller if written by the cpu and executed by flash controller if ic p writes the command. from flash controller locked state, must be the third command written to this register to initiate mass erase). enable flash sector protect register access. downloaded from: http:///
19-4572; rev 0; 4/09 flash control register definitions zlf645 series flash mcus product specification 77 flash status register the flash status (fstat) register (see table 34 ) indicates the current state of the flash controller. this register can be read an y time. the read-only flash status (fstat) ? register shares its register file address with the write-only flash control (fctl) register. table 34. flash status register (fstat) flash page select register the flash page select (fps) register (see table 35 ) shares address space with the flash sector protect (fsec) register. unless the flas h controller is in locked state and its flash control (fctl) register is written with 5eh , writes to this address target the flash page select (fps) register. the fps register is used to select one page w ithin the flash main memory or information block for programming or eras ure depending upon whether its if en bit is 0 or 1 respec- tively. each flash main memory page contains 512 bytes of flash memory. during a page erase operation to the main memory, the page th at will be erased is the one containing the 512 flash memory locations where bits 15 throug h 9 of their addresses is equal to bits 6 through 0 of fps register. for main memory programming operations, bits 15 through 9 of the address to be programmed must equal bits 6 through 0 of the fps register for the flash controller to execute the operation. for page erase or programming operations to the flashs information block as indicated by the ifen bit being 1, the programming or bits 7 6 5 4 3 2 1 0 field reserved fstat reset 00000000 r/w rrrrrrrr address bank f, register address: 01h bit position value description [7:6] reserved reads as 0s. [5:0] 000000 000001 000010 000011 000100 001xxx 010xxx 100xxx fstat flash cont roller status flash controller locked. ? first unlock command received (73h written). ? second unlock command received (8ch written). ? flash controller unlocked. sector protect register selected. program operation in progress. ? page erase operation in progress. ? mass erase operation in progress. downloaded from: http:///
19-4572; rev 0; 4/09 flash control register definitions zlf645 series flash mcus product specification 78 page erase command must be initiated by the icp. information block page erase or pro- gramming operations initiated by the cpu are ignored by the flash controller. in the case of an information block programming or page erase operation initiated by the icp, the fps register must first be programmed with 83h to point to page 3 of the information block or else the operation will be ignored by the flash controller. for information block programming through the icp, bits 12 through 6 of the address must equal ? bits 6 through 0 of the fps register for the flash controller to ex ecute the operation. table 35. flash page select register (fps) flash sector protect register the flash sector protect (fsec) register (see table 36 ) address is shared with the flash page select (fps) register. it is accessed by first writing 5eh to the flash control (fctl) register with the flash controll er in locked state, and then writing to the register file address location given for the flash page select (fps) register. the fsec register selects which of the eight av ailable flash memory sectors is to be pro- tected from cpu initiated programming or pa ge erase operations. for icp initiated pro- gramming or page erase operations, the settin gs within the fsec regi ster are ignored by the flash controller. the reset state of each sect or protect bit in the fsec register is its unprotected state or 0 value. after a sector is protected by setting its corresponding regis- ter bit to 1, it cannot be unprotected (the regi ster bit cannot be cleared) without powering down the device. bits 7 6 5 4 3 2 1 0 field ifen page reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank f, register address: 02h bit position value description [7] 01 ifen information area enable operation to be performed on flash main memory. operation to be performed on flash information area. [6:0] 01 page page select this 7-bit field identifies the flash main memory page for page erase and page unlocking. program memory address[15:9] = page[6:0]. ? the least significant 2 bits of page identifies the flash information page for page erase and page unlocking. the upper significant bits must be logic 0s. downloaded from: http:///
19-4572; rev 0; 4/09 flash control register definitions zlf645 series flash mcus product specification 79 table 36. flash sector protect register (fsec) flash frequency high and low byte registers the flash frequency high and low byte registers ( table 37 and table 38 ) combine to form a 16-bit value, ffreq, to control timi ng for flash program and erase operations. the 16-bit binary flash frequency value must contain the system clock frequency (in khz) and is calculated usin g the following equation: programming the flash frequency high and low byte registers as per the formula ? provides a flash programming time of approximately 30 ? s and an erase time of ? approximately 10 ms. flash programming and erasure is not suppo rted for system clock frequencies below ? 1 mhz or above 8 mhz. the flash frequency high and low byte registers must be loaded with the correct value to en sure proper operation of the device. bits 7 6 5 4 3 2 1 0 field sprot7 sprot6 sprot5 sprot4 sprot3 sprot2 sprot1 sprot0 reset 00000000 r/w r / wr / wr / wr / wr / wr / wr / wr / w address bank f, register address 02h bit position value description [7:0] sprot7-sprot0 sector protection each bit corresponds to an 16-page flash sector. for the zlf645xxxxx64, all bits are used. only bits 3-0 are used in the zlf645xxxxx32. for icp initiated operations, no sector protection exists. ffreq[15:0] ffreqh[7:0], ffreql[7:0] ?? system clock frequency (hz) 1000 ------------------------------------------------------------------------------- == caution: downloaded from: http:///
19-4572; rev 0; 4/09 flash control register definitions zlf645 series flash mcus product specification 80 table 37. flash frequency high byte register (ffreqh) flash controller functions summary the flash controller performs its functions, direct ed by either the icp interface or by the cpu through instruction codes. table 39 lists the functions that will or will not be performed by the flash controlle r, according to whether the cpu or icp is the initiator, whether the operation is performed on the fl ashs main memory or information block, and whether either of the two read/write prot ect bits of user option byte 1 have been enabled or not. bits 7 6 5 4 3 2 1 0 field ffreqh reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank f, register address: 03h bit position value description [7:0] ffreqh flash frequency high byte high byte of the 16-bit flash frequency value. table 38. flash frequency low byte register (ffreql) bits 7 6 5 4 3 2 1 0 field ffreql reset 0 r/w r/w address bank f, register address: 04h bit position value description [7:0] ffreql flash frequency low byte low byte of the 16-bit flash frequency value. downloaded from: http:///
19-4572; rev 0; 4/09 flash control register definitions zlf645 series flash mcus product specification 81 table 39. flash controller functions summary control source flash memory block program read page erase mass erase flash protect icp main memory yes yes yes yes yes 1 information area page 3 only page 3 only page 3 only no yes 2 cpu through instruction code main memory yes yes yes no no 3 information area no no no no no 3 notes 1. flprot1 = 0, cannot read or writ e lowest half of memory. flrwp = 0, cannot read or write entire main memory. 2. flrwp/flprot1 = 0, cannot write or erase page 3. 3. flprot1 = 0, no effect. flrwp = 0, no effect. downloaded from: http:///
19-4572; rev 0; 4/09 flash byte programming interface zlf645 series flash mcus product specification 82 flash byte programming interface using the zlf645s flash byte programming interface, the on-chip flash controller can be bypassed, allowing direct control of the flash signals through registered values of certain of the zlf645s gpio pins. bypassing the flash controller allows faster row programming algorithms to be used by controlling the flash programming signals directly. this method is beneficial when programming a large number of devices and can be used for flash programming by third party vendo rs who manufacture gang programmers. for more information on how to use this interface, refer to third-party flash programming support for z8 crimzon flash parts , available for download at www.maxim-ic.com . enabling the flash byte programming interface the flash byte programming interface is en abled by writing three bytes to the icp ? interface: 1. 80h initiates auto-baud calculation of the icp interface data and clock rate. 2. f0h icp write test mode register command. 3. 04h data to be written to the test mo de register. this enables the flash byte programming interface. since flash byte programmin g interface is enabled with the zlf645 mcu in icp mode, the cpu clock will stop and no cpu accesses to the flash memory will occur. flash byte programming interface flash access restrictions the types of flash access allowed to th e flash memory through the flash byte programming interface is qualified similar to the icp, by the settings of the flash memory protection bits in user option byte 1. if e ither of the flash protect bits are set, the program memory has to be mass erased before full read/program access is allowed to either the main memory or in formation area page 3 sections of the flash memory, respec- tively. flash memory access allowed through the flash byte progra mming interface is summarized in table 40 . note: downloaded from: http:///
19-4572; rev 0; 4/09 flash byte programm ing interface flash access restrictions zlf645 series flash mcus product specification 83 table 40.flash byte programming functions summary flash memory block program read page erase mass erase flash protect option bits main memory yes yes yes yes flrwp=1, flprot1=1 main memory no no no yes flrwp=0, flprot1=x main memory yes 1 yes 1 yes 1 yes flrwp=1, flprot1=0 information area yes 2 yes 2 yes 2 yes flrwp=1, flprot1=1 information area no yes 2 no yes flrwp=1, flprot1=0 information area no yes 2 no yes flrwp=0, flprot1=1 notes 1. program, read, and page erase access is limited to the upper half address space of the main memory only. 2. only page 3 of the information area is accessibl e for program, read, and page erase operations. downloaded from: http:///
19-4572; rev 0; 4/09 infr ared learning amplifier zlf645 series flash mcus product specification 84 infrared learning amplifier the zlf645 mcus infrared learning amplifier allows you to detect and decode infrared transmissions directly from the output of the receiving diode without the need for external circuitry (see port 3 on page 23). an ir diode can be connected to the ir amplifier as displayed in figure 21 . when the ir amplifier is enabled and an input current is detected on port 3, pin 1 (p31), the ir ampli- fier outputs a logical high value. when the input current is below the switching threshold of the ir amplifier, the amplif ier outputs a logical low value. within the mcu, the ir amp output goes to the capture/timer lo gic, which can be ? programmed to demodula te the ir signal. the ir amplifie r output can also be read by the cpu, or drive the port 3, pin 4 (p34) output if write-only register bit pcon[0] is set to 1. for the maximum current input that is clearl y recognized by the zlf645 as a 0 and the minimum current input that is cl early recognized as a 1, see i detlo and i dethi ? parameters, respectively, in table 80 on page 165. the ir learning amplifier can demodulate sign als up to a frequency of 500 khz. a special mode exists that allows you to capture the third, fourth, and fifth edges of the ir amplifier output and generate an interrupt. for details on programming the timers to demodulate a received signal, see timers on page 99. figure 21. learning amplification circuitry within the zlf645 flash mcu v dd d1 photodiode p31 of mcu downloaded from: http:///
19-4572; rev 0; 4/09 universal a synchronous receiver/transmitter zlf645 series flash mcus product specification 85 universal asynchronous receiver/ transmitter the universal asynchronous receiver/transmitter (uar t) is a full-duplex ? communication channel capable of handling asynchronous data transfers. the two uarts use a single 8-bit data mo de with selectable parity. the uart interface when enabled uses the gpio pins p07 for the uart transmit and p32 for the uart receive. the features of the uart include: 8-bit asynchronous data transfer selectable even- and odd-parity generation and checking one or two stop bits separate transmit and receive interrupts framing, overrun, and break detection separate transmit and receive enables 8-bit baud rate generator baud rate generator timer mode uart operational during halt mode table 41. uart control registers address (hex) reset 12-bit bank 8-bit register description mnemonic page no 0f1 all f1 uart receive/transm it data register urdata/ utdata xxh 95 0f2 all f2 uart status register ust 0000_0010b 95 0f3 all f3 uart control register uctl 00h 97 0f4 all f4 uart baud rate generator constant register bcnst ffh 98 downloaded from: http:///
19-4572; rev 0; 4/09 architecture zlf645 series flash mcus product specification 86 architecture the uarts consist of three primary functional blocks: transmitter , receiver , and baud rate generator . the uart transmitter and receiver fu nction independently, but employ the same baud rate and data format. figure 22 displays the uart architecture. operation the uart channel can be used to communicate with a master microprocessor or a slave microprocessor, both of which exhibit transmit and receive functionality. you can either operate the uart channel by polling the uart status register or via interrupts. the uart remains active during halt mode. if ne ither the transmitter nor the receiver is enabled, the uart baud rate generator can be used as an additional timer. the uart contains a noise filter for the receiver that can be enabled by the user. figure 22. uart block diagram receive shifter receive data register rxd system bus transmit data register transmit shift register parity generator transmitter control status register control register txd baud rate generator downloaded from: http:///
19-4572; rev 0; 4/09 operation zlf645 series flash mcus product specification 87 data format 1 1 lsb msb 0 2 idle stateof line stop bit(s) data eld bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 start 1 1 lsb msb 0 2 idle stateof line stop bit(s) data eld bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 7 start the uart transmits and receives data in an 8-b it data format, with the least significant bit (lsb) occurring first. an even- or odd-parity bit can be op tionally added to the data stream. each character begins with an active low start bit and ends with either 1 or 2 active high stop bits. figure 23 and figure 24 display the asynchronous data format employed by the uarts with or without parity, respectively. transmitting data using polled method follow the steps below to transmit data using the polled method of operation: 1. write to the baud rate generator constant (bcnst) register, address 0f4h , to set the appropriate baud rate. 2. write 0 to bit 6 of the p01m register. 3. write to the uart control register (uctl) to: (a) set the transmit enable bit, uctl[7], to enable the uart for data transmission. (b) if parity is appropriate, set the parity enable bit, uctl[4] to 1 and select either even- or odd-parity (uctl[3]). figure 23. uart asynchronous data format without parity figure 24. uart asynchronous data format with parity downloaded from: http:///
19-4572; rev 0; 4/09 operation zlf645 series flash mcus product specification 88 4. check the transmit status register bit, ust[2], to determine if the transmit data ? register is empty (indicated by 1). if empty, continue to step 6 . if the transmit data register is full (indicated by 0), continue to monitor the ust[2] bit until the transmit data register is availa ble to receive new data. 5. write the data byte to the uart transmit data register, 0f1h . the transmitter ? automatically transfers the data to the internal transmit shift register and transmits the data. 6. to transmit additional bytes, return to step 4 . 7. before disabling the transmitter, read the transmit completion status bit, ust[1]. if ust[1]=0, continue to monitor the bit until it changes to 1, which indicates that all data in the transmit data and internal shift registers has been transmitted. data written while the transmit enable bit is clear (uctl[7] =0) will not be transmitted. data written while the transmit data status bit is clear (ust[2]=0) overwrites the ? previous value written, so the previous writte n value will not be transmitted. disabling the uart transmitter while the transmit comple tion status bit is clear (ust[1]=0) can corrupt the byte being transmitted. transmitting data usi ng interrupt-driven method the uart transmitter interrupt indicates the availa bility of the transmit data register to accept new data for transmission. follow the steps below to configure the uar t for interrupt-driven data transmission: 1. write to the bcnst register to set the appropriate baud rate. 2. write 0 to bit 6 of the p01m register. 3. execute di instruction to disable interrupts. 4. write to the interrupt control registers to enable the uart transmitter interrupt and set the appropriate priority. 5. write to the uart control register to: (a) set the transmit enable bit (uctl bit 7) to enable the uart for data transmission. (b) enable parity, if appropriate, and select either even- or odd-parity. 6. execute an ei instruction to enable interrupts as the transmit buffer is empty, an ? interrupt is immediately executed. 7. write the data byte to the uart transmit da ta register. the transmitter automatically transfers the data to the internal transm it shift register and transmits the data. 8. execute the iret instruction to return fro m the interrupt service routine (isr) and wait for the transmit data register to again become empty. caution: downloaded from: http:///
19-4572; rev 0; 4/09 operation zlf645 series flash mcus product specification 89 9. before disabling the transmitter, read the transmit completion status bit, ust[1]. if ust[1]=0, continue to monitor the bit until it changes to 1, which indicates that all data in the transmit data and internal shift registers has been transmitted. data written while the transmit enable bit is clear (uctl[7] =0) will not be transmitted. data written while the transmit data status bit is clear (ust[2]=0) overwrites the pre- vious value written, so the previous written va lue will not be transmitted. disabling the uart transmitter while the transmit completio n status bit is clear (ust[1]=0) can ? corrupt the byte being transmitted. receiving data using the polled method follow the steps below to configur e the uart for polled data reception: 1. write to the bcnst register to set the appropriate baud rate. 2. write to the uart control register (uctl) to: (a) set the receive enable bit (uctl[ 6]) to enable the uar t for data reception (b) enable parity (if appropriate) and select either even- or odd-parity 3. check the receive status bit in the uart st atus register, bit ust[7], to determine if the receive data register contains a valid data byte (indicated by a 1). if ust[7] is set to 1 to indicate availa ble data, continue to step 4 . if the receive data register is empty (indicated by a 0), continue to monitor the ust[7] bit awaiting reception of the valid data. 4. read data from the uart receive data register. 5. return to step 3 to receive additional data. receiving data using the interrupt-driven method the uart receiver interrupt indicates the availability of new data (as well as error ? conditions). follow the steps below to configure the uar t receiver for interru pt-driven operation: 1. write to the uart brg constant registers to set the appropriate baud rate. 2. execute di instruction to disable interrupts. 3. write to the interrupt control registers to enable the uart receiver interrupt and set the appropriate priority. 4. clear the uart receiver interrupt in th e applicable interrupt request register. 5. write to the uart control register (uctl) to: (a) set the receive enable bit (uctl[ 6]) to enable the uar t for data reception (b) enable parity, if appropriate, and select either even- or odd-parity 6. execute an ei instruc tion to enable interrupts. caution: downloaded from: http:///
19-4572; rev 0; 4/09 operation zlf645 series flash mcus product specification 90 the uart is now configured for interrupt-driven data reception. when the uart ? receiver interrupt is detected, the associated isr performs the following: 1. checks the uart status register to determin e the source of the interrupt, whether it is an error, break, or received data. 2. reads the data from the uart receive data register, if the interrupt was caused by data available. 3. clears the uart receiver interrupt in th e applicable interrupt request register. 4. executes the iret instruction to retu rn from the isr and await more data. uart interrupts the uart features separate interrupts for the transmitter and the receiver. in addition, when the uart primary functionality is disab led, the brg can also function as a basic timer with interrupt capability. when the uart is set to run at higher baud ra tes, the uart receivers service routine may not have enough time to read and manipu late all bits in the uart status register (especially bits generating error conditions) fo r a received byte before the next byte is received. you can devise your own hand-shaking protocol to prevent the transmitter from transmitting more data while current data is being serviced. transmitter interrupts the transmitter generates a single interrupt wh en the transmit status bit, ust[2], is set to 1. this indicates that the transmitter is ready to accept new data for transmission. the transmit status interrupt occurs after the internal transmit shift register has shifted the first bit of data out. at this poin t, the transmit data register can be written with the next char- acter to send. this provides 7 bit periods of latency to load the transmit data register before the transmit shift register completes shifting the current ch aracter. writing to the uart transmit data register clears the ust[ 2] bit to 0. the in terrupt is cleared by ? writing a 0 to the transmit data register. receiver interrupts the receiver generates an interrupt when any of the following occurs: a data byte is received and availa ble in the uart receive data register this interrupt can be disabled independent of the other receiver interrupt sources. the received data interrupt occurs once the r eceive character has been received and placed in the receive data register. software must respond to this received data available condition before the next character is comple tely received to avoid an overrun error. the interrupt is cleared by reading from the uart receive data register. a break is received a break is detected when a 0 is sent to the receiver for the full byte plus the parity and stop bits. af ter a break is detected, it will interrupt note: downloaded from: http:///
19-4572; rev 0; 4/09 operation zlf645 series flash mcus product specification 91 immediately if there is no valid data in the receive data register. if data is present in the receive data register, an interrupt will occur after the uart receive data register is read. an overrun is detected an overrun occurs when a byte of data is received while there is valid data in the uart receive data register that has not been read by the user. the interrupt will be generated when the user reads the uart receive data register. the interrupt is cl eared by reading the uart receive data register. when an overrun error occurs, the add itional data byte will not ov erwrite the data currently stored in the uart receive data register. a data framing error is detected a data framing error is detected when the first stop bit is 0 instead of 1. when configured for 2 stop bits, a data framing error is only detected when the first stop bit is 0. a fra ming error interrupt is generated when the framing error is detected. reading the uart receive data register clears the interrupt. ensure that the transmitter uses the same stop bit configuration as the receiver. uart overrun errors when an overrun error condition occurs the uart prevents overwriting of the valid data currently in the receive data register. the br eak detect and overrun status bits are not displayed until after the va lid data has been read. after the valid data has been re ad, the uart status (ust) regi ster is updated to indicate the overrun condition (and break detect, if ap plicable). the ust[7] bit is set to 1 to ? indicate that the receive data register contai ns a data byte. however, because the overrun error occurred, this byte may not contain valid data and must be ignored. the break detect bit, ust[3], indicates if the overrun was ca used by a break condition on the line. after reading the status byte indicating an overrun e rror, the receive data register must be read again to clear the error bits is the uart stat us 0 register. updates to the receive data reg- ister occur only when the next data word is received. uart data and error handling procedure figure 25 on page 92 displays the recommended procedure for use in uart receiver interrupt service routine. note: downloaded from: http:///
19-4572; rev 0; 4/09 operation zlf645 series flash mcus product specification 92 figure 25. uart receiver in terrupt service routine flow receiver interrupt yes the rda bit and resets the error bits read status receiver ready read data that clears errors? discard data read data no downloaded from: http:///
19-4572; rev 0; 4/09 operation zlf645 series flash mcus product specification 93 baud rate generator interrupts if the brg interrupt enable is set, the uart receiver interrupt asserts when the uart baud rate generator reloads. this action a llows the brg to function as an additional counter if the uart functi onality is not employed. uart baud rate generator the uart baud rate generator creates a lo wer frequency baud rate clock for data ? transmission. the input to the baud rate generator is the system clock. the uart baud rate constant register contains an 8-bit ba ud rate divisor value (bcnst[7:0]) that sets the data transmission rate (baud rate) of the uar t. for programmed register values other than 00h , the uart data rate is calcul ated using the below equation: when the uart baud rate low register is programmed to 00h , the uart data rate is calculated as follows: when the uart baud rate generator is used as a general-purpose counter, the counters time-out period can be computed as follows based upon the counters clock input being a divide by 16 of the system clock and the maximum count value being 255: the relationship between the xtal1 clock freq ue ncy and the system clock frequency must be considered before making this computation and is dependent upon the programming of bit 2 of user option byte 1 as well as th e programming of bit 0 of the smr register. depending on the programmed values, the system clock frequency can be a divide by 1, a divide by 2, or a divide by 16 of the xtal1 clock. when the uart is disabled, the brg can functio n as a basic 8-bit timer with interrupt on time-out. uart data rate (bps) = system clock frequency (hz) 16 x uart baud rate divisor value (bcnst) uart data rate (bps) = system clock frequency (hz) 4096 time-out period (us) = 16 x uart baud rate divisor value (bcnst) system clock frequency (mhz) note: downloaded from: http:///
19-4572; rev 0; 4/09 operation zlf645 series flash mcus product specification 94 follow the steps below to configure the brg as a timer with interrupt on time-out: 1. disable the uart by clearing the receive and transmit enable b its, uctl[7:6] to 0. 2. load the appropriate 8-bit count value into the uart baud rate generator constant register. the count frequency is the system clock frequency (in hz) divided by 16. 3. enable the baud rate generator timer function and associ ated interrupt by setting the baud rate generator bit (uctl bit 0) in the uart control register to 1. when ? configured as an 8-bit timer, the count value, instead of the reload value, is read, and the counter begins counting down from its initial programmed value. on timing out (reaching a value of 1), if the time-out interrupt is enabled, an interrupt will be ? produced. the counter will then reload its programmed st art value and begin counting down again. ? table 42 lists a number of bcnst register settings at various baud rates and system clock frequencies. table 42. bcnst register settings examples target uart data rate (baud) system clock = 4 mhz, ? crystal clock = 8 mhz system clock = 3 mhz, ? crystal clock = 6 mhz 2400 bcnst = 01101000 ? actual baud rate = 2403 bcnst = 01001110 ? actual baud rate = 2403 4800 bcnst = 00110100 ? actual baud rate = 4807 bcnst = 00100111 ? actual baud rate = 4807 9600 bcnst = 00011010 ? actual baud rate = 9615 bcnst = 00010100 ? actual baud rate = 9375 19200 bcnst = 00001101 ? actual baud rate = 19230 bcnst = 00001010 ? actual baud rate = 18750 downloaded from: http:///
19-4572; rev 0; 4/09 uart receive da ta register/uart transmit data zlf645 series flash mcus product specification 95 uart receive data register/u art transmit data register the uart receive/transmit data register (see table 43 ) is used to send and retrieve data from the uart channel. when the uart receives a data byte, it can be read from this register. the uart receive interrupt is clea red when this register is used. data ? written to this register is transmitted by the uart. uart status register the uart status register (see table 44 ) displays the status of the uart. bits [6:3] are cleared by reading the uart receive/transmit register ( f1h ). table 43. uart receive/transmit data register (urdata/utdata) bit 7 6 5 4 3 2 1 0 field uart receive/transmit reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: f1h; linear: 0f1h bit position description [7:0] uart receive/transmit when read, returns received data. when written, transmits written data. table 44. uart status register (ust) bit 7 6 5 4 3 2 1 0 field receive status parity error overrun error framing error break transmit data transmit complete noise filter reset 00000010 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: f2h; linear: 0f2h bit position value description [7] ? 01 receive status set when data is received; cleared when urdata is read. uart receive data register empty. uart receive data register full. downloaded from: http:///
19-4572; rev 0; 4/09 uart control register zlf645 series flash mcus product specification 96 uart control register the uart control register controls the uart. in addition to setting b it 5, you must also set appropriate bit in the interrupt mask register (see table 65 on page 133). this register is not reset after a stop mode recovery. [6] 01 parity error set when a parity error occurs; cleared when urdata is read. no parity error occurs. parity error occurs. [5] 01 overrun error set when an overrun error occurs; cleared when urdata is read. no overrun error occurs. overrun error occurs. [4] 01 framing error set when a framing error occurs; cleared when urdata is read. no framing error occurs. framing error occurs. [3] ? 01 break set when a break is detected; cleared when urdata is read. no break occurs. break occurs. [2] 01 transmit data status set when the uart is ready to transmit; cleared when trdata is written. do not write to the uart transmit data register. uart transmit data register ready to receive additional data. [1] 01 transmit completion status data is currently transmitting. transmission is complete. [0] ? read 01 noise filter detects noise during data reception. no noise detected. noise detected. write 01 turn off noise filter. turn on noise filter. bit position value description note: downloaded from: http:///
19-4572; rev 0; 4/09 uart baud ra te generator constant register zlf645 series flash mcus product specification 97 uart baud rate generator constant register the uart baud rate generator determines the frequency at wh ich uart data is received and transmitted. this baud rate is determined by the fo llowing equation: table 45. uart control register (uctl) bit 7 6 5 4 3 2 1 0 field transmitter enable receiver enable uart interrupts enable parity enable parity select send break stop bits baud rate generator reset 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: f3h; linear: 0f3h bit position value description [7] ? 01 transmitter disabled. transmitter enabled. [6] ? 01 receiver disabled. receiver enabled. [5] ? 01 uart interrupts disabled. uart interrupts enabled. [4] ? 01 parity disabled. parity enabled. [3] ? 01 even parity selected. odd parity selected. [2] 0 1 no break is sent. send break (force tx output to 0). [1] ? 01 one stop bit. two stop bits. [0] ? 01 baud rate generator when the transmitter and receiver are disabled, the brg can be used as an additional timer. wh en setting this bit, clear bits [7:6] in this register. also set bit [5] if an interr upt is required when the brg is reloaded. brg used as baud rate generator for uart. brg used as timer. uart data rate (bps) = system clock frequency (hz) 16 x uart baud rate divisor value (bcnst) downloaded from: http:///
19-4572; rev 0; 4/09 uart baud ra te generator constant register zlf645 series flash mcus product specification 98 the system clock is usually the crystal clock divided by 2. when the uart baud rate gen- erator is used as an additional timer, a read from this register retu rns the actual value of the count of the brg in progress and not the reload value. see table 46 . this register is not reset after a stop mode recovery. table 46. uart baud rate generator constant register (bcnst) bit 7 6 5 4 3 2 1 0 field baud rate generator constant reset 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: f4h; linear: 0f4h bit position description [7:0] ? baud rate generator constant when read, returns the actual timer count value (when uctl[0]=1). when written, sets the baud rate generator constant. the actual baud rate frequency = xtal (32 x bcnst ). note: downloaded from: http:///
19-4572; rev 0; 4/09 timers zlf645 series flash mcus product specification 99 timers the zlf645 mcu infrared timer features a 16- bit and an 8-bit counter/timer, each of which can be used simultaneously for transm itting. both timers can be used for demodu- lating an input carrier wave and share a single input pin. figure 26 displays the counter/timer architecture , which is designed to help unburden the program from coping with real-time problems like generating complex waveforms or receiving and demodulating co mplex waveforms and pulses. in addition to the 16-bit and 8-bit timers, the uarts baud rate generator can be used as an additional 8-bit timer when the uart receiv er is not in use (for more details, see ? universal asynchronous receiver/transmitter on page 85). figure 26. counter/timers block diagram hi16 lo16 tc16h tc16l hi8 lo8 tc8h tc8l 8-bit timer 8 16-bit timer 16 timer 16 timer 8/16 sclk timer 8 and/or logic clock divider glitch filter edge detect circuit 8 8 8 8 8 16 8 8 8 1248 downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 100 table 47 summarizes the timer control registers. so me timer functions can also be affected by control registers for ot her peripheral functions. counter/timer functional blocks the zlf645 mcu infrared timer co ntains a glitch filter for removing noise from the input when demodulating an input carrier. each ti mer features its own demodulating mode and can be simultaneously used to generate a signal output. th e t8 timer has the ability to ? capture only one cycle of a carrier wave of a high-frequency waveform. input circuit depending on the setting of register bits p3 m[2:1] and ctr1[6], th e timer/counter input circuit monitors one of the following conditions: the p31 digital signal, if ctr1[6]=0 and p3m[2:1]=00. the p31 analog comparator output, if ctr1[6]=0 and p3m[2:1]=01. the p31 ir amplifier output, if ctr1[6]=0 and p3m[2]=1. the p20 digital signal, if ctr1[6]=1. table 47. timer control registers address (hex) 12-bit bank 8-bit register description mnemonic reset page no d00 d 00 counter/timer 8 control register ctr0 000 0_ 0 0 00b 119 d01 d 01 timer 8 and timer 16 common functions ctr1 00 0 0_00 0 0b 121 d02 d 02 counter/timer 16 control register ctr2 000 0_ 0 000b 124 d03 d 03 timer 8/timer 16 control register ctr3 00 0 0_ 0xxxb 126 d04 d 04 counter/timer 8 low hold register tc8l 00h 118 d05 d 05 counter/timer 8 high hold register tc8h 00h 117 d06 d 06 counter/timer 16 low hold register tc16l 00h 117 d07 d 07 counter/timer 16 high hold register tc16h 00h 116 d08 d 08 timer 16 capture low register lo16 00h 116 d09 d 09 timer 16 capture high register hi16 00h 115 d0a d 0a timer 8 capture low register lo8 00h 115 d0b d 0b timer 8 capture high register hi8 00h 114 downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 101 based on register bits ctr1[5:4], a pulse is generated at when a rising edge, falling edge, or any edge is detected. glitche s in the input signal are filtered out if they are shorter than the glitch filter width specified in register bits ctr1[3:2]. figure 27 displays the input cir- cuit. the timers can be configured to operate in following modes: t8 transmit mode t8 demodulation mode t16 transmit mode t16 demodulation mode ping-pong mode t8 transmit mode before t8 is enabled, the output of t8 depends on ctr1, bit 1. if the bit is 0, t8_out is 1; if it is 1, t8_out is 0. see figure 28 . figure 27. counter/timer input circuit glitch filter 8 sclk reserved 4 sclk 00 10 11 01 edge detection ctr1[0] ctr1[1] 00 01 11 reserved 10 falling edgerising edge p31 comp. ir amp. p30 i ref p20 01 + + 01 ctr1[5:4] ctr1[3:2] ctr1[6] p3m[2] p3m[1] 0 1 downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 102 figure 28. transmit mode flowchart load tc8l reset t8_out load tc8h set t8_out enable t8 no yes set time-out status bit (ctr0, bit 5) and generate timeout_int if enabled 1 0 t8 (8-bit) transmit mode t8_enable bit set ctr0, bit 7 no yes ctr1, bit 1 value 1 load tc8l reset t8_out load tc8h set t8_out enable t8 reset t8_enable bit set time-out status bit (ctr0 bit 5) and generate timeout_int if enabled no no t8_timeout yes yes single pass? modulo-n single pass 0 t8_out value t8_timeout downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 103 when t8 is enabled, the outp ut t8_out switches to the initial value (ctr1, bit 1). if the initial value (ctr1, bit 1) is 0, tc8l is load ed; otherwise, tc8h is loaded into the coun- ter. in single-pass mode (ctr0, bit 6), t8 counts down to 0 and stops, t8_out toggles, the time-out status bit (ctr0, bit 5) is set, and a time-out interrupt can be generated if it is enabled (ctr0, bit 1). in modulo-n mode, on reaching terminal count , t8_out is toggled, but no interrupt is generated. from that point, t8 loads a new count (if the t8_out level now is 0), tc8l is loaded; if it is 1, tc8h is loaded. t8 coun ts down to 0, toggles t8_out, and sets the time-out status bit (ctr0, bit 5), thereby gene rating an interrupt if enabled (ctr0, bit 1). one cycle is thus completed. t8 then lo ads from tc8h or tc8l according to the ? t8_out level and repeats the cycle. see figure 29 . you can modify the values in tc8h or tc8l at any time. the new values take effect when they are loaded. an initial count of 1 is not allowed (a non-fu nction occurs). an initial count of 0 causes tc8 to count from 0 to ffh to feh . figure 29. 8-bit counter/timer circuits z8 lxmc data bus z8 lxmc data bus positive edge negative edge ctr0 data bit 2 irq4 ctr0 data bit 1 t8_out tc8l tc8h clock select sclk ctr0 data bits [4:3] clock hi8 lo8 8-bit counter t8 (tc8) caution: downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 104 1. the h suffix denotes hexadecimal values. 2. transition from 0 to ffh is not a time-out condition. using the same instructions for stopping the co unter/timers and setting the status bits is not recommended. two successive commands are necessary. first, the counter /timers must be stopped. second, the status bits must be reset. these commands are required as it takes one counter/ timer clock interval for the initiated event to actually occur. see figure 30 and figure 31 . figure 30. t8_out in single-pass mode figure 31. t8_out in modulo-n mode notes: caution: tc8h counts counter enable command; t8_out switches to its initial value (ctr1 data bit 1) t8_out toggles; time-out interrupt t8_out tc8l tc8h tc8l tc8l t8_out toggles counter enable command; t8_out, switches to its initial value (ctr1 data bit 1) time-out interrupt time-out interrupt tc8h downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 105 t8 demodulation mode you must program tc8l and tc8h to ffh . after t8 is enabled, when the first edge (ris- ing, falling, or both depending on ctr1 bits [5 :4]) is detected, it starts to count down. when a subsequent edge (rising, falling, or both depending on ctr1 bits [5:4]) is detected during counting, the current value of t8 is complemented and put into one of the capture registers. if it is a positive edge, data is put into lo8; if it is a negativ e edge, data is put into hi8. from that point, one of the edge detect status bits (ctr1, bits [1:0]) is set, and an interrupt can be generated if enabled (ctr0, b it 2). meanwhile, t8 is loaded with ffh and starts counting again. if t8 reaches 0, the time-out status bit (ctr0, bi t 5) is set, and an interrupt can be generated if enabled (ctr0, b it 1). t8 then continues counting from ffh( see figure 32 on page 106). downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 106 when bit 4 of ctr3 is enabled, the flow of the demodulation sequence is altered. ? the third edge makes t8 active, and the fourth and fifth edges are captured. ? the capture interrupt is activated after the fi fth event occurs. this mode is useful for ? capturing the carrier duty cycle as well as the frequency at which the first cycle is ? corrupted. see figure 33 and figure 34 . figure 32. demodulation mode count capture flowchart t8 (8-bit) no no yes yes t8_enable (set by user) edge present? what kind of edge? pos neg t8 ?? ? lo8 ? t8 ??? hi8 %ff ?? t8 count capture downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 107 figure 33. demodulation mode flowchart t8 (8-bit) demodulation mode t8_enable ctr0, d7? no yes first edge present? nono t8_enable bit set? yes set edge present status bit and trigger data capture int. if enabled no %ff tc8 yes enable tc8 edge present? disable t8 yes t8 time out? yes set time-out status bit and trigger time out int. if enabled no continue counting downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 108 figure 34. demodulation mode fl owchart with bit 4 of ctr3 set t8 (8-bit) demodulation mode t8_enable ctr0 bit 7 no yes third edge present no no t8_enable bit set yes no ffh tc8 yes enable tc8 disable t8 yes t8 time out yes set time-out status bit and trigger time out interrupt if enabled no continue counting fifth edge present yes set edge present status capture interrupt if enabled fourth edge present set edge present status bit and trigger data downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 109 t16 transmit mode in normal or ping-pong mode, the output of t16 when not enabled depends on ctr1, bit 0. if this bit is set to 0, t16_out is a 1; if set to 1, t16_out is 0. you can force the output of t16 to either 0 or 1 whet her it is enabled or no t by programming ctr1 bits [3:2] to a 10 or 11. when bit 4 of ctr3 is set, the t16 output does not update. however, time-out interrupts (flags) are still updated. in addition, the t8 carrier is not disrupted by timing out of the t16 timer. when t16 is enabled, a value of (tc16h * 256) + tc16l is loaded, and t16_out is switched to its initial value (ctr1, bit 0). when t16 counts down to 0, t16_out is ? toggled (in normal or ping-pong mode), an interrupt (ctr2, bit 1) is generated (if enabled), and a status bit (ctr2, bit 5) is set. see figure 35 . global interrupts override this function as described in the interrupts on page 127. if t16 is in single-pass mode, it is stopped at this point (see figure 36 on page 110). if it is in modulo-n mode, it is loaded with tc16h * 256 + tc16l, and the counting continues (see figure 37 on page 110). you can modify the values in tc16h and tc16l at any time. the new values take effect when they are loaded. figure 35. 16-bit counter/timer circuits positive edge negative edge ctr2 data bit 2 irq3 ctr2 data bit 1 t16_out tc16 tc16 clock select sclk ctr2 data bits [4:3] clock 16-bit counter t16 (tc16) hi16 lo16 z8 lxmc data bus z8 lxmc data bus note: downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 110 do not load these registers at the time the values are to be loaded in to the counter/timer to ensure known operation. an initial count of 1 is not allowed. an initial count of 0 causes t16 to count from 0 to fffeh . transition from 0 to ffffh is not a time-out condition. t16 demodulation mode you must program tc16l and tc16h to ffh . after t16 is enabled, and the first edge (rising, falling, or both depending on ctr1 bi ts [5:4]) is detected, t16 captures hi16 and lo16, reloads, and begins counting. figure 36. t16_out in single-pass mode figure 37. t16_out in modulo-n mode caution: tc16h * 256 + tc16l counts counter enable command; t16_out, switches to its initial value (ctr1 data bit 0) t16_out toggles, time-out interrupt t16_out tc16h * 256 + tc16l tc16h * 256 + tc16l tc16h * 256 + tc16l counter enable command; t16_out, switches to its initial value (ctr1 data bit 0) time-out interrupt time-out interrupt t16_out toggles, t16_out toggles, downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 111 if bit 6 of ctr2 is 0 when a subsequent edge (rising, falling, or both depending on ? ctr1 bits [5:4]) is detected during counting, the current count in t16 is complemented and loaded into hi16 and lo16. when data is captured, one of the edge detect status bits (ctr1, bit 1; bit 0) is set, and an interrupt is generated if enabled (ctr2, bit 2). t16 is loaded with ffffh and starts again. this t16 mode is generally used to measure space time, the length of time between bursts of carrier signal (marks). if bit 6 of ctr2 is 1 t16 ignores the subsequent edges in the input signal and continues counting down. a time-out of t8 causes t16 to capture its current value and generate an interrupt if enabled (ctr2, bit 2). in this case, t16 does not relo ad and continues count- ing. if ctr2 bit 6 is toggled (by writing a 0 th en a 1 to it), t16 captures and reloads on the next edge (rising, falling, or both depending on ctr1 bits [5:4]), continuing to ignore sub- sequent edges. this t16 mode generally measu res mark time, the length of an active car- rier signal burst. if t16 reaches 0, t16 continues counting from ffffh . meanwhile, a status bit (ctr2 bit 5) is set, and an interrupt time-out can be generated, if enabled (ctr2 bit 1). ping-pong mode ping-pong mode is only valid in transmit mode . t8 and t16 must be programmed in single-pass mode (ctr0, bit 6; ctr2, bit 6), and ping-pong mode must be pro- grammed in ctr1 bits [3:2]. you can begin the operation by enabling either t8 or t16 (ctr0, d7 or ctr2, d7). for ex ample, if t8 is enabled, t8 _out is set to this initial value (ctr1, bit 1). according to t8_out's level, tc8h or tc8l is loaded into t8. af ter the terminal count is reached, t8 is disabled, and t16 is enabled. t16_out th en switches to its initial value (ctr1, bit 0), data from tc16h and tc16l is loaded, and t16 starts to count. after t16 reaches the terminal count, it stops, t8 is enab led again, repeating the entire cycle. inter- rupts can be allowed when t8 or t16 reaches terminal control (ctr0, bit 1; ctr2, bit 1). to stop the ping-pong operation, write 00 to bits ctr1 bits [3:2]. see figure 38 on page 112. enabling ping-pong operatio n while the counter/timers are running may cause ? intermittent counter/timer function. disable the counter/timers and reset the status flags before instituting this operation. note: downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 112 initiating ping-pong mode first, ensure that both co unter/timers are not running. follow the steps below to initiate the ping-pong mode: 1. set t8 into single-pass mode (ctr0, bit 6) 2. set t16 into single-pass mode (ctr2, bit 6) 3. set the ping-pong mode (ctr1 bits [3:2]) these instructions are not consecutiv e and can occur in random order. 4. finally, start ping-pong mode by enabling either t8 (ctr0, d7) or t16 (ctr2, d7). the initial value of t8 or t16 must not be 1 . if you stop the timer and restart the timer, re load the initial value to avoid an unknown ? previous value. during ping-pong mode the enable bits of t8 and t16 (ctr0, d7; ctr2, d7) are set and cleared alternately by hardware. the time-out bits (ctr0, bit 5; ctr2, bit 5) are set every time the counter/ ? timers reach the terminal count. timer output the output logic for the timers is displayed in figure 39 on page 113. p34 is used to output t8_out when bit 0 of ctr0 is set. p35 is u sed to output the value of t16_out when bit figure 38. ping-pong mode diagram enable tc8 time-out enable tc16 time-out ping-pong ctr1 data bits [3:2] downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer functional blocks zlf645 series flash mcus product specification 113 0 of ctr2 is set. when bit 6 of ctr1 is set, p36 outputs the logic combination of t8_out and t16_out via bits [4:5] of ctr1. figure 39. timer output circuit mux mux mux mux p34 p36 p35 p34_internal p36_internal p35_internal ctr0 data bit 0 ctr1 data bit 6 ctr2 data bit 0 ctr1 data bit 3 ctr1 data bit 2 t16_out t8_out ctr1 data bits [5:4] and/or/nor/nand logic downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 114 counter/timer registers the following sections describe each of the timer/counter registers in detail. timer 8 capture high register the timer 8 capture high register (see table 48 ) holds the captured data from the output of the 8-bit counter/timer 0. this register contains the number of counts when the input signal is 1. this register is not reset after a stop mode recovery. timer 8 capture low register the timer 8 capture low register (see table 49 on page 115) holds the captured data from the output of the 8-bit counter/timer 0. typically, this register contains the number of counts when the input signal is 0. this register is not reset after a stop mode recovery. table 48. timer 8 capture high register (hi8) bit 7 6 5 4 3 2 1 0 field t8_capture_hi reset 0 0 0 0 0 0 0 0 r/w rrrrrrrr address bank d: 0bh; linear: d0bh bit position value description [7:0] 0hhCffh t8_capture_hi reads return captured data. writes have no effect. note: note: downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 115 timer 16 capture high register the timer 16 capture high register (see table 50 ) holds the captured data from the ? output of the 16-bit counter/timer 16. this re gister contains the most significant byte (msb) of the data. this register is not reset after a stop mode recovery. table 49. timer 8 capture low register (lo8) bit 7 6 5 4 3 2 1 0 field t8_capture_lo reset 0 0 0 0 0 0 0 0 r/w rrrrrrrr address bank d: 0ah; linear: d0ah bit position value description [7:0] 0hhCffh t8_capture_lo read returns captured data. writes have no effect. table 50. timer 16 capture high register (hi16) bit 7 6 5 4 3 2 1 0 field t16_capture_hi reset 0 0 0 0 0 0 0 0 r/w rrrrrrrr address bank d: 09h; linear: d09h bit position value description [7:0] 0hhCffh t16_capture_hi read returns captured data. writes have no effect. note: downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 116 timer 16 capture low register the timer 16 capture low register (see table 51 ) holds the captured data from the ? output of the 16-bit counter/timer 16. this register contains the least significant byte (lsb) of the data. this register is not reset after a stop mode recovery. counter/timer 16 high hold register the counter/timer 16 high hold register (see table 52 ) contains the high byte of the value loaded into the t16 timer. this register is not reset after a stop mode recovery. table 51. timer 16 capture low register (lo16) bit 7 6 5 4 3 2 1 0 field t16_capture_lo reset 0 0 0 0 0 0 0 0 r/w rrrrrrrr address bank d: 08h; linear: d08h bit position value description [7:0] 0hhCffh t16_capture_lo read returns captured data . writes have no effect. table 52. counter/timer 16 high hold register (tc16h) bit 7 6 5 4 3 2 1 0 field t16_data_hi reset 0 0 0 0 0 0 0 0 r/w r / wr / wr / wr / wr / wr / wr / wr / w address bank d: 07h; linear: d07h bit position value description [7:0] 0hhCffh t16_data_hi read/write data. note: note: downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 117 counter/timer 16 low hold register the counter/timer 16 lo w hold register (see table 53 ) contains the low byte of the value loaded into the t16 timer. this register is not reset after a stop mode recovery. counter/timer 8 hi gh hold register the counter/timer 8 high hold register (see table 54 ) contains the value to be counted while the t8 output is 1. this register is not reset after a stop mode recovery. table 53. counter/timer 16 low hold register (tc16l) bit 7 6 5 4 3 2 1 0 field t16_data_lo reset 0 0 0 0 0 0 0 0 r/w r / wr / wr / wr / wr / wr / wr / wr / w address bank d: 06h; linear: d06h bit position value description [7:0] 0hhCffh t16_data_lo read/write data. table 54. counter/timer 8 high hold register (tc8h) bit 7 6 5 4 3 2 1 0 field t8_level_hi reset 0 0 0 0 0 0 0 0 r/w r / wr / wr / wr / wr / wr / wr / wr / w address bank d: 05h; linear: d05h bit position value description [7:0] 0hhCffh t8_level_hi read/write data. note: note: downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 118 counter/timer 8 low hold register the counter/timer 8 low hold register (see table 55 ) contains the value to be counted while the t8 output is 0. this register is not reset after a stop mode recovery. table 55. counter/timer 8 low hold register (tc8l) bit 7 6 5 4 3 2 1 0 field t8_level_lo reset 0 0 0 0 0 0 0 0 r/w bank d: 04h; linear: d04h address r / wr / wr / wr / wr / wr / wr / wr / w bit position value description [7:0] 0hhCffh t8_level_lo read/write data. note: downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 119 counter/timer 8 control register the counter/timer 8 co ntrol register (see table 56 ) controls the timer function of the ? t8 timer. writing 1 to ctr0[5] is the only way to rese t the terminal count status condition. reset this bit before using/en abling the counter/timers. ? ? you must be careful when using the or or and commands to manipulate ctr0, bit 5 and ctr1, bits 0 and 1 (demodulation mode). these instructions use a read-modify- write sequence in which the current status from the ctr0 and ctr1 registers is ored or anded with the designated value an d then written back into the registers. example: when the status of bit 5 is 1, a timer reset condition occurs. table 56. counter/timer 8 control register (ctr0) bit 7 6 5 4 3 2 1 0 field t8_enable single- pass/ modulo-n time_out t8 _clock capture_int _mask counter_int_mask p34_out reset 000 0 0 0 00 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank d: 00h; linear: d00h caution: note: downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 120 bit position value description [7] 01 t8_enable disable/enable the t8 counter. (note: this register bit duplicates the function of register bit 6 of the ctr3 register). disables the t8 counter if bit 6 of the ctr3 register is also 0. enables the t8 counter if bit 6 of the ctr3 register is also 0 and has no effect if the t8 counter is already enabled by bit 6 of the ctr3 register being 1. [6] 01 single-pass/modulo-n modulo-n mode. counter reloads the initial value when terminal count is reached. single-pass mode. counter stops when the terminal c ount is reached. [5] read 01 write 01 time_out this bit is set when the t8 terminal count is reached. no counter time-out occurred. counter time-out occurred. no effect. reset flag to 0. software must reset this flag before using counter/timers. [4:3] ? 0001 10 11 t8 _clock select the t8 input clock frequen cy.these bits are not reset upon stop mode recovery. sclk sclk 2 sclk 4 sclk 8 [2] ? 01 capture_int_mask disable/enable interrupt when data is captured into either lo8 or hi8 on a positive or negative edge detection in demodulation mode. this bit is not reset up on stop mode recovery. disable data capture interrupt. enable data capture interrupt. [1] ? 01 counter_int_mask disable/enable t8 time-out inte rrupt. this bit is not reset upon stop mode recovery. disable time-out interrupt. enable time-out interrupt. [0] 01 p34_out select normal i/o or t8 output function for port 3, pin 4. p34 as port output. t8 output on p34. downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 121 t8 and t16 common functions register the t8 and t16 common functions register (ctr1) controls the functions in common with timer 8 and timer 16. table 57 describes the bits for this register. be careful to differentiate transmit mode from demodulation mode, as set by ctr1[7]. the functions of ctr1[6:0] and ctr2[6] are different depending on which mode is selected. do not change from one mode to another without first disabling the counter/timers. table 57. timer 8 and timer 16 common functions register (ctr1) bit 7 6 5 4 3 2 1 0 field mode p36 out/ demodulator input t8/t16 logic/ edge detect transmit submode/ glitch filter initial timer 8 out/ rising edge initial timer 16 out/ falling edge reset 00 0 000 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank d: 01h; linear: d01h bit position value description [7:0] 01 mode selects the timer mode for signal transmission or demodulation. transmit mode. demodulation mode. [6] 01 transmit mode p36 outselect normal i/o or timer output on port 3, pin 6. p36 acts as normal i/o port output. p36 acts as combined timer 8/timer 16 output. 01 demodulation mode demodulator inputselect po rt 2, pin 0 or port 3, pin 1 as the counter/timer input. p31 acts as the demodulator input. if imr[2] = 1, a p31 event can also generate an irq1 interrupt. to prevent this, clear imr[2] or select p20 as input instead. p20 acts as the demodulator input. note: downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 122 bit position value description [5:4] 0001 10 11 transmit mode t8/t16 logicdefines how the timer 8/ti mer 16 outputs are combined logically. ? these bits are not reset upon stop mode recovery. output is t8 and t16. output is t8 or t16. output is t8 nor t16. output is t8 nand t16. 0001 10 11 demodulation mode edge detectdefine the behavior of the edge detector. falling edge detection. rising edge detection. falling and rising edge detection. reserved. [3:2] 0001 10 11 transmit mode submode selectionselect normal or ping-pong mode operation, or force t16 output. when these bits are written to 00b (normal mode) or 01b ? (ping-pong mode), t16_out assumes the opposite state of bit ctr1[0] until the timer begins counting. normal operation. writing 00 terminat es ping-pong mode, if it is active. ping-pong mode. force t16_out = 0 force t16_out = 1 0001 10 11 demodulation mode glitch filterdefine the maximum glit ch width to be rejected by the ? counter/timer. no filter. 4 sclk cycle filter. 8 sclk cycle filter. reserved. downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 123 ? bit position value description [1] 01 transmit mode initial timer 8 outselect the initial t8_out state when timer 8 is enabled. while the timer is disabled, the opposite st ate is asserted on the pin to ensure that a transition occurs when the timer is enabled. changing this bit while the counter is enabled can cause unpredictable output on t8_out. t8_out transitions from high to low when timer 8 is enabled. t8_out transitions from low to high when timer 8 is enabled. read 01 write 01 demodulation mode rising edgeindicates whether a rising edge was detected on the input signal. write 1 to this flag to reset it. no rising edge detection. rising edge detection. no effect. reset flag to 0. [0] 01 transmit mode initial timer 16 outin normal or ping-p ong mode, this bit selects the initial t16_out state when timer 16 is enable d. while the timer is disabled, the opposite state is asserted on the pin to ensure that a transition occurs when the timer is enabled. changing this bit while the counter is enabled can cause unpredictable output on t16_out. if ctr1[3]=0, t16_out transitions from high to low when timer 16 is enabled. if ctr1[3]=0, t16_out transitions from low to high when timer 16 is enabled. read 01 write 01 demodulation mode falling edgeindicates whether a falling ed ge was detected on the input signal. write 1 to this flag to reset it. no falling edge detection. falling edge detection. no effect. reset flag to 0. downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 124 counter/timer 16 control register table 58 describes the bits for the counter/timer 16 co ntrol register (ctr2). table 58. counter/timer 16 control register (ctr2) bit 7 6 5 4 3 2 1 0 field t16_enable single/ modulo-n time_out t16 _clock capture_int _mask counter_int _mask p35_out reset 0000 00 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank d: 02h; linear: d02h bit position value description [7] 01 t16_enable disable/enable the t16 counter. (note: this register bit duplicates the function of register bit 7 of the ctr3 register). disables the t16 counter if bit 7 of the ctr3 register is also 0. enables the t16 counter if bit 7 of the ctr3 register is also 0 and has no effect if the t16 counter is already enabl ed by bit 7of the ctr3 register being 1. [6] 01 transmit mode (ctr1[7]=0) single/modulo-nselects timer 16 terminal count action. modulo-n mode. t16 reload s the initial value wh en terminal count is reached. single-pass mode. t16 stops when th e terminal count is reached. 01 demodulation mode (ctr1[7]=1) enable single-edge capture. see t16 demodulation mode on page 110. timer 16 captures and reloads on all edges. timer 16 captures and reloads on first edge only. [5] read 01 write 01 time_out this bit is set when the t16 terminal count is reached. time_outthis bit is set when the t16 terminal count is reached. no counter time-out occurs. counter time-out occurred. no effect. reset flag to 0. software must reset this flag befo re using counter/timers. downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 125 timer 8/timer 16 control register the timer 8/timer 16 counter/timer register allows the start time of the t8 and t16 counters to be synchronized by simultaneously pr ogramming bits 7 and 6 to 1. it also can freeze the t16 output value and change t8 demodulation mode to capture one cycle of a carrier. table 59 briefly describes the bits for this bank d register. [4:3] ? 0001 10 11 t16 _clock select t16 input clock frequency. these bits are not reset upon stop mode recovery. sclk sclk 2 sclk 4 sclk 8 [2] ? 01 capture_int_mask disable/enable interrupt when data is captured into either lo16 or hi16 upon a positive or negative edge detection in demodulation mode. this bit is not reset upon stop mode recovery. disable data capture interrupt. enable data capture interrupt. [1] 01 counter_int_mask disable/enable t16 time-out interrupt. disable t16 time-out interrupt. enable t16 time-out interrupt. [0] 01 p35_out select normal i/o or t8 out put function for port 3, pin 5. p35 as port output. p35 is t16 output. bit position value description downloaded from: http:///
19-4572; rev 0; 4/09 counter/timer registers zlf645 series flash mcus product specification 126 table 59. timer 8/timer 16 control register (ctr3) bit 7 6 5 4 3 2 1 0 field t16_enable t8_enable sync_mode t16_out disable t8 demodulate reserved reset 0 0 000x x x r/w r/w r/w r/w r/w r/w address bank d: 03h; linear: d03h bit position value description [7] ? 01 t16_enable disable/enable the t16 counter. (note: this register bit duplicates the function of register bit 7 of the ctr2 register). disables the t16 counter if bit 7 of the ctr2 register is also 0. enables the t16 counter if bit 7 of the ctr2 register is also 0 and has no effect if the t16 counter is already enabled by bit 7of the ctr2 register being 1. [6] 01 t8_enable disable/enable the t8 counter. (not e: this register bit duplicates the function of register bit 7of the ctr0 register). disables the t8 counter if bit 7o f the ctr0 register is also 0. enables the t8 counter if bit 7of the ctr0 register is also 0 and has no effect if the t8 counter is already enabled by bit 7of the ctr0 register being 1. [5] sync_mode when enabled, the first pulse of timer 8 (the carrier) is always synchronized with timer 16 (the demodulated signal). it can always provide a full carrier pulse. this bit is not reset upon stop mode recovery. 01 disable sync mode. enable sync mode. [4] t16_out disable set this bit to disable toggling of the timer 16 output. time- out interrupts ar e still generated. this bit is not reset upon stop mode recovery. 01 t16 toggles normally. t16 toggle is disabled. [3] ? t8 demodulate (capture one cycle) this bit is not reset upon stop mode recovery. 01 t8 captures events normally. t8 becomes active on the third edge, captures events on the fourth and fifth edges, and generates an interrupt on the fifth edge. after a t8 time-out the event count resets to 0 and the fourth and fifth edges are captured again. [2:0] reserved always reads 111b. must be written to 1. downloaded from: http:///
19-4572; rev 0; 4/09 interrupts zlf645 series flash mcus product specification 127 interrupts the zlf645 mcu features six interrupts (see table 61 on page 129). these interrupts are maskable and pr ioritized (see figure 40 on page 128). the six interrupt sources are divided as follows: three sources are claimed by port 3 lines p33:p31 two by the counter/timers (see table 61 ) one for low-voltage detection p32 and uart receiver share the same interrupt. only one interrupt can be selected as a source. when the uart receiver is enabled, p 32 is no longer used as an interrupt source. the uart transmit interrupt and uart baud ra te interrupt use the same interrupt as the p33 interrupt. the user selects which source tr iggers the interrupt. when bit 7 of uctl is 1, the uart transmit interrupt is the source. when bit 7 of uctl is 0 and bit 5 of uctl is 1, the brg interrupt is selected. the interrupt mask register (globally or individually) enables or disables the six interrupt requests. the source for irq1 is determined by bit 1 of the port 3 mode register (p3m) and bit 4 of the smr4 register. if p3m[1]=0 (digital mode) and smr4[4 ]=0, pin p33 is the irq1 source. if p3m[1]=1 (analog mode) or smr4[4]=1 (smr interrupt en abled), the output of the stop mode recovery source logic is used as the source for the inte rrupt. for more details, see stop mode recovery interrupt on page 144. table 60. interrupt control registers address (hex) reset 12-bit bank 8-bit register description mnemonic page no 0f9 all f9 interrupt priority register ipr xxh 130 0fa all fa interrupt request register irq 00h 131 0fb all fb interrupt mask register imr 0xxx_xxxxb 133 downloaded from: http:///
19-4572; rev 0; 4/09 interrupts zlf645 series flash mcus product specification 128 figure 40. interrupt block diagram uctl bits 5 & 6 = 11 irq register (bits 6 & 7) interrupt request interrupt mask register 5 vector select global interrupt enable interrupt request priority logic interrupt priority register interrupt edge select timer 16 p31 irq2 irq3 irq1 irq0 irq4 irq5 p32 uart r x p33 stop mode recovery source uart brg interrupt uctl bits 7, 6, and 0 = 001 uart t x uctl bits 5 and 7 = 11 p3m[1] or smr4[4] timer 8 low-voltage detection 01 01 01 01 downloaded from: http:///
19-4572; rev 0; 4/09 interrupts zlf645 series flash mcus product specification 129 when more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the interrupt priority register . an interrupt machine cycle activates when an interrupt request is grante d. as a result, all subsequent interrupts are disabled, and the program counter and status flags are saved. the cy cle then branches to the program memory vector location reserved for that interrupt. all zlf645 mcu interrupts are vectored throug h locations in the program memory. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked, and the interrupt request register is polled to determine which of the interrupt requests require service. an interrupt resulting from an1 is mapped in to irq2, and an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 can be rising, falling, or both edge triggered. these interrupts are user-programmable. the software can poll to identify the state of the pin. table 61. interrupt types, sources, and vectors name source vector location (program memory) comments irq0 p32, uart rx 0,1 exter nal (p32), rising, falling edge triggered irq1 p33, uart tx, brg, smr event 2, 3 external (p33), falling edge triggered irq2 p31 4, 5 external (p31), rising, falling edge triggered irq3 timer 16 6, 7 internal irq4 timer 8 8, 9 internal irq5 low-voltage detection 10, 11 internal downloaded from: http:///
19-4572; rev 0; 4/09 interrupt priority register zlf645 series flash mcus product specification 130 programming bits for the interru pt edge select are located in the irq register (r250), ? bit 6 and bit 7. table 62 provides the configuration. interrupt priority register the interrupt priority register (see table 63 ) defines which interrupt holds the highest ? priority. interrupts are divided into three groups of twogroup a, group b, and group c. ipr bits 4, 3, and 0 determine which interrupt group has prior ity. for example, if interrupts irq5, irq1, and irq0 occur simultaneously when ipr[4:3, 0]=001b, the interrupts are serviced in the following order: irq1, irq0, irq5. ipr bits 5, 2, and 1 determine which interrupt within each group has higher priority. table 62. interrupt request register irq bit interrupt edge 7 6 irq2 (p31) irq0 (p32) 00f f 01f r 10r f 11r / f r / f note: f = falling edge; r = rising edge. table 63. interrupt priority register (ipr) bit 7 6 5 4 3 2 1 0 field reserved group a priority group priority [2:1] group b priority group c priority group priority [0] reset xxxxxx x x r/w www ww address bank independent: f9h; linear: 0f9h bit position value description [7:6] ? reserved reads are undefined; writes must be 00b. [5] ? 01 group a priority (irq3, irq5) irq5 > irq3 irq3 > irq5 downloaded from: http:///
19-4572; rev 0; 4/09 interrupt request register zlf645 series flash mcus product specification 131 interrupt request register bit 7 and bit 6 of the interr upt request register (see table 64 ) are used to configure the edge detection of the interrupts for port 3, bit 1 and port 3, bit 2. the remaining bits (5 through 0) indicate the status of the interrupt. when an interrupt is serviced, the hardware automatically clears the bit to 0. writing 1 to any of these bits generate s an interrupt if the appropriate bits in the interrupt mask register are enabled. writing 0 to these bits clears the interrupts. {[4:3], [0]} ? 000001 010 011 100101 110 111 group priorityreserved c > a > b a > b > c a > c > b b > c > a c > b > a b > a > c reserved [2] 01 group b priority (irq0, irq2) irq2 > irq0 irq0 > irq2 [1] 01 group c priority (irq1, irq4) irq1 > irq4 irq4 > irq1 table 64. interrupt request register (irq) bit 7 6 5 4 3 2 1 0 field interrupt edge irq5 irq4 irq3 irq2 irq1 irq0 reset 00000000 r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: fah; linear: 0fah bit position value description [7:6] ? 0001 10 11 interrupt edge p31 ??? p32 ? p31 ??? p32 ? p31 ??? p32 ? p31 ???? p32 ?? bit position value description downloaded from: http:///
19-4572; rev 0; 4/09 interrupt request register zlf645 series flash mcus product specification 132 the irq register is protected from change until an ei instruction is executed once. [5] ? read 01 write 01 irq5 (low-voltage detection) interrupt did not occur. interrupt occurred. clear interrupt. set interrupt. [4] read 01 write 01 irq4 (t8 counter) interrupt did not occur. interrupt occurred. clear interrupt. set interrupt. [3] read 01 write 01 irq3 (t16 counter) interrupt did not occur. interrupt occurred. clear interrupt. set interrupt. [2] read 01 write 01 irq2 (port 3 bit 1 input) interrupt did not occur. interrupt occurred. clear interrupt. set interrupt. [1] read 01 write 01 irq1 (port 3 bit 3 input/smr event/uart t x /uart brg) interrupt did not occur. interrupt occurred. clear interrupt. set interrupt. [0] read 01 write 01 irq0 (port 3 bit 2 input/uart r x ) interrupt did not occur. interrupt occurred. clear interrupt. set interrupt. bit position value description note: downloaded from: http:///
19-4572; rev 0; 4/09 interrupt mask register zlf645 series flash mcus product specification 133 interrupt mask register bits [5:0] are used to enable the interrupt. bit 7 is the status of the master interrupt. when reset, all interrupts are disabled. when writin g 1 to bit 7, you must also execute the ei instruction to enable interrupts (see table 65 ). table 65. interrupt mask register (imr) bit 7 6 5 4 3 2 1 0 field master interrupt enable reserved irq5 enable irq4 enable irq3 enable irq2 enable irq1 enable irq0 enable reset 0 x xxxxxx r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: fbh; linear: 0fbh bit position value description [7] 01 master interrupt enable use only di and ei instructions to alter this bit. always disable interrupts (di instruction) before wr iting this register. all interrupts are disabled. interrupts are enabled/disabled individually in bits [5:0]. [6] 0 reserved reads are undefined; must be written to 1. [5] 0 1 disables irq5. enables irq5. [4] 0 1 disables irq4. enables irq4. [3] 0 1 disables irq3. enables irq3. [2] 0 1 disables irq2. enables irq2. [1] 0 1 disables irq1. enables irq1. [0] 0 1 disables irq0. enables irq0. downloaded from: http:///
19-4572; rev 0; 4/09 clock zlf645 series flash mcus product specification 134 clock zlf645 mcus on-chip oscillator has a high -gain, parallel-resonant amplifier for ? connecting to a crystal, ceramic resonator, or any suitable external clock source ? (xtal1 = input, xtal2 = output). crystal specification the crystal must be at cut, 1 mhz to 8 mh z (maximum), with a series resistance (rs) less than or equal to 100 ? . the on-chip osci llator can be driven wi th a suitable external clock source. the crystal must be connected across xtal 1 and xtal2 pins using the recommended capacitors from each pin to ground. the typical capacitor value is 10 pf for 8 mhz. check with the crystal supplier fo r the optimum capacitance. maxims ir mcu supports crystal, resonator, and oscillator. most resonators have a frequency tolerance of less than 0.5%, which is enough for a remote control application. resonator has a very fast startup time, which is around few hundred microseconds. most crystals have a frequency tolerance of less than 50 ppm (0.005%). however, crystal needs longer startup time than the resonator. the large loading capac itance slows down the oscillation startup time. clock o scillation must be stable before the cpu begins instruction execution. if oscillation is not present or not stab le before the chip completes timeout of its power-on reset (por) period, the chips behavior could be indeterminate. figure 41. oscillator configuration c1c2 xtal1 xtal2 xtal1 xtal2 ceramic resonator or crystal c1, c2 = 10 pf * f = 8 mhz external clock *note: preliminary value, including pin parasitics. xtal1 xtal2 ceramic resonator f = 8 mhz downloaded from: http:///
19-4572; rev 0; 4/09 crystal 1 oscillator pin (xtal1) zlf645 series flash mcus product specification 135 maxim ? recommends not to use more than 10 pf loading capacitor for the crystal. if the stray capacitance of the pcb or the crystal is high, the loading capacitance c1 and c2 must be reduced furthe r to ensure stable os cillation before the t por (por time is typically 5-6 ms. for more details, see table 81 on page 169.). for stop mode recovery operation, bit 5 of smr register allows you to select the stop mode recovery delay, which is the t por . if stop mode recovery delay is not selected, the mcu executes instruction immediately after it wakes up from the stop mode. if resonator or crystal is used as a clock source then stop mode recovery delay needs to be selected (bit 5 of smr = 1). for both resonator and crystal oscillator, the oscillation ground must go directly to the ground pin of the microcontroller. the oscillation ground must use the shortest distance from the microcontroller ground pin and it must be isolated from other connections. crystal 1 oscillator pin (xtal1) the crystal 1 oscillator time- based input pin connects a pa rallel-resonant crystal or ceramic resonator to the on-chip oscillator inpu t. additionally, an op tional external single- phase clock can be connected to the on-chip oscillator input. crystal 2 oscillator pin (xtal2) the crystal 2 oscillator time -based output pin connects a parallel-resonant crystal or ceramic resonant to the on-chip oscillator output. internal clock signals (sclk and tclk) the cpu and internal peripherals are driven by the internal sclk signal during normal execution. during halt mode, the interrupt logic is driven by the internal tclk signal. the frequency of these signals with respect to the xtal1 cloc k input is selectable either by programming bit 2 of the flashs user option byte 1 for no division of the xtal1 ? signal input, dividing it by a factor of two, and optionally by applying an additional ? divide-by-16 prescaler enabled through smr register bit 0 (see table 69 on page 146), as displayed in figure 42 . selecting the divide-by-16 prescaler reduces device power draw- during normal operation and halt mode. th e prescaler is disabled by a por or stop mode recovery. downloaded from: http:///
19-4572; rev 0; 4/09 internal clock signals (sclk and tclk) zlf645 series flash mcus product specification 136 figure 42. sclk/tclk circuit osc scl k tclk 0 1 01 /2 /16 smr[0] user option byte 1, bit #2 downloaded from: http:///
19-4572; rev 0; 4/09 reset and power management zlf645 series flash mcus product specification 137 reset and power management the zlf645 mcu provides the fo llowing reduced-power mod es, power monitoring, and ? reset features: voltage brownout standby stops the oscillator and inte rnal clock when the power level drops below the vbo low voltage dete ct point. initiates a power-on reset when power is restored above the vbo detect point. stop mode stops the clock and oscillator, re duces the mcu supply current to a very low level until a power-on reset or stop mode recovery occurs. halt mode stops the internal clock to the cpu until an enabled interrupt request is received. voltage detection optionally sets a flag if a low- or high-voltage condition occurs. the low-voltage detection flag can gene rate an interrupt request, if enabled. power-on reset starts the oscillator and internal clock, and initiali zes the system to its power-on reset defaults. watchdog timer optionally generates a power-on reset if the program fails to ? execute the wdt instruction with in a specified time interval. stop mode recovery restarts the oscillator and intern al clock, and initializes most of the system to its power-on reset defaults . some register values are not reset by a ? stop mode recovery. for supply current values under various conditions, see dc characteristics on page 165. figure 43 on page 138 displays the power-on reset sources. table 66 lists control ? registers for reset and power management featur es. some features are affected by registers described in other chapters. table 66. reset and power management registers address (hex) reset 12-bit bank 8-bit register description mnemonic page no d0c d 0c low-voltage detection register lvd 1 11 1 _1000 b 140 f0a f 0a stop mode recovery register 4 smr4 x x x 0 _ 0 0 0 0b 156 f0b f 0b stop mode recovery register smr 0 0 1 0_ 0 0 00 b 146 f0c f 0c stop mode recovery register 1 smr1 00h 150 f0d f 0d stop mode recovery register 2 smr2 x 0 x 0 _ 0 0 x xb 152 note: downloaded from: http:///
5-clock filter clr2* reset 18-clock reset generator reset xtal internal rc oscillator internal reset active high wdt tap select 1 2 34 clk por/wdt wdt/por counter chain clr1 v dd vbo + _ low operating voltage detection vdd wdt 1 0 12 ns glitch filter from stop mode recovery smr[5] * clr1 and clr2 enable the wdt/por and 18 clock reset timers, respectively, on a low-to-high input transition. 19-4572; rev 0; 4/09 reset and power management zlf645 series flash mcus product specification 138 figure 43. resets and watchdog timer f0e f 0e stop mode recovery register 3 smr3 x0h 155 f0f f 0f watchdog timer mode register wdtmr 0 0 0 0 _ 1 1 0 1b 142 table 66. reset and power management registers (continued) address (hex) reset 12-bit bank 8-bit register description mnemonic page no downloaded from: http:///
19-4572; rev 0; 4/09 vo ltage brownout standby zlf645 series flash mcus product specification 139 voltage brownout standby an on-chip voltage comparator ci rcuit (vbo) checks that the v dd is at the required level for correct operation of the device in term s of flash memory reads. a second on-chip comparator circuit (subvbo) checks that the v dd level is high enough for proper opera- tion of the vbo circuit. if the v dd level drops below the vbo trip point, the zlf645 will be held in a reset state as long as v dd remains below this trip point value, and the xtal1 and xtal2 oscillator circuitry will be disab led thereby stopping the clock input to the zlf645 and saving power. if the v dd level continues to drop below the subvbo trip point, the zlf645 will remain in a reset st ate and the vbo comparator circuit will be ? disabled for further power savings. when th e power level returns to a value above the vbo trip point, the device performs a power-on reset and functions normally. stop mode stop instruction turns off the internal clock and external crystal o scillation, thus reduc- ing the mcu supply current to a very low le vel. for stop mode current specifications, see table 80 on page 165. to enter stop mode, first flush the instructi on pipeline to avoid suspending execution in mid-instruction. execute a nop instruction (opcode = ffh ) immediately before the appropriate sleep instruction, as given below: ff nop ; clear the pipeline ? 6f stop ; enter stop mode stop mode is terminated only by a reset, such as wdt time-out, por, or one of the stop mode recovery events as described in stop mode recovery event sources on page 144. this condition causes the processor to r estart the application program at address 000ch . unlike a normal por or wdt reset, a stop mode recovery reset does not reset the contents of some registers and bits. register bits not reset by a stop mode recovery are highlighted in grey in the register tables. regi ster bit smr[7] is set to 1 by a stop mode recovery. halt mode halt instruction turns off the internal cp u clock, but not the xtal oscillation. ? the counter/timers, uart, and interrupts (i rq0, irq1, irq2, irq3, irq4, and irq5) remain active. the devices are recovered by in terrupts, either extern ally or internally ? generated. an interrupt reques t must be executed (enabled ) to exit halt mode. after the interrupt service routine, th e program continues from the instruction after halt mode. downloaded from: http:///
19-4572; rev 0; 4/09 voltage detection zlf645 series flash mcus product specification 140 to enter halt mode, first flush the instructio n pipeline to avoid suspending execution in mid-instruction. execute a nop instruction (opcode = ffh ) immediately before the appropriate sleep instruction, as given below: ? ff nop ; clear the pipeline ? 7f halt ; enter halt mode power consumption during halt mode can be reduced by first setting smr[0]=1 to enable the divide-by-16 clock prescaler. voltage detection the low-voltage detection register (lvd, register 0ch at the expanded register bank 0dh ) provides an option to monitor the v dd voltage. the voltage detection is enabled when bit 0 of lvd register is set. af ter voltage detection is enabled, the v dd level is ? monitored in real time. the hvd flag (bit 2 of the lvd register) is set only if v dd is higher than v hvd. the lvd flag (bit 1 of the lvd register) is set only if v dd is lower than the v lvd . when voltage detection is enabled, the lvd flag also triggers irq5. ? the irq bit 5 latches the low voltage condition until it is cleared by instructions or reset. the irq5 interrupt is served if it is enabled in the imr register. otherwise, bit 5 of irq register is latched as a flag only. do not modify register p01m while checkin g a low voltage condition. switching noise from port 0 can trigger the lvd flag. table 67. low-voltage detection register (lvd) bit 7 6 5 4 3 2 1 0 field reserved high-battery detect low-battery detect voltage detect enable reset 11111 0 0 0 r/w rrrrr r r r / w address bank d: 0ch; linear: d0ch bit position value description [7:3] reservedreads 11111b. must be written to 1. [2] ? 01 hvd clear. high-voltage detected (v dd >v hvd) note: downloaded from: http:///
19-4572; rev 0; 4/09 power-on reset timer zlf645 series flash mcus product specification 141 power-on reset timer when power is initially applied to the device, a timer circuit clocked by a dedicated ? on-board rc-oscillator provides the por timer function. the por timer circuit is a one- shot timer that keeps the internal re set signal asserted long enough for v dd and the ? oscillator circuit to stabilize befo re instruction execution begins. the reset timer is triggered by one the following conditions: initial power-on or recovery from a vbo/standby condition. stop mode recovery (if register bit smr[5] = 1). watchdog timer time-out. smr[5] can be cleared to 0 to bypass the por timer on a stop mode recovery. this must only be done when using an external clock that does not require a startup delay. failure of an application to provide a stable oscillating clock input to xtal1 before the end of the zlf645s por period may result in an indetermin ate chip behavior and must be avoided. for details on the por timing range, see table 81 on page 169 in the electrical characteristics chapter. watchdog timer the watchdog timer (wdt) is a retriggerabl e one-shot timer that resets the z8 lxmc cpu if it reaches its terminal count. the wd t must initially be en abled by executing the wdt instruction. on subsequent executi ons of the wdt instruction, the wdt is ? refreshed. the wdt circuit is driven by an on-board rc-oscillator. the wdt instruction affects the zero (z), sign (s ), and overflow (v) flags. the por clock source is an internal rc-oscillator. bits 0 and 1 of the wdt register ? control a tap circuit that determines the minimum time-out period. bit 2 determines whether the wdt is active during halt, and b it 3 determines wdt activity during stop mode. bits 4 through 7 are reserved (see table 68 on page 142). this register is accessible only during the first 60 processor cycles (120 xtal clocks) from the execution of the first instruction after power-on reset, watchdog tim er reset, or a stop mode recovery (see fast stop mode recovery ). after this point, the register ca nnot be modified by any means. the [1] ? 01 lvd clear. low-voltage detected (v dd 19-4572; rev 0; 4/09 watchdog timer zlf645 series flash mcus product specification 142 wdtmr register cannot be read. the register is located in bank f of the expanded reg- ister group at address location 0fh . this register is not reset after a stop mode recovery. although not explicitly shown above, if any two bits of b its 6 through 4 are programmed to 1 or if all three bits are programmed to 0, th en the time-out period depends on bits 1 and 0 only as shown for the [6:4]=000 case. using the watchdog timer as a stop mode recovery source as mentioned previously, timeout of the watchdog timer generates a chip reset that removes the zlf645 from stop mode. this feat ure is used to configure the zlf645 to automatically exit stop mode, once it is in stop mode. this is done within a set maxi- mum period of time based upon the watchdog timer timeout setting. in this way, the table 68. watchdog timer mode register (wdtmr) bit 7 6 5 4 3 2 1 0 field time-out select wdt during stop mode wdt during halt mode time-out select reset 0 0 0 0 1 1 0 1 r/w wwww w w w w address bank f: 0fh; linear: f0fh bit position value description [7] reserved reads are undefined; must write 0000. [3] ? 01 wdt during stop mode determines if wdt is active during stop mode. off. wdt active during stop mode. [2] 01 wdt during halt mode determines if wdt is active during halt mode. see figure 43 on page 138. off. wdt active during halt mode. [6:4], [1:0] 000_00 000_01 000_10 000_11 001_xx 010_xx 100_xx time-out select selects the wdt time period (see note below). 5 ms minimum 10 ms minimum 20 ms minimum 80 ms minimum 320 ms minimum 1, 280 ms minimum 5,120 ms minimum note: note: downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 143 zlf645 is configured to periodically enter and exit stop mode until some action is nec- essary by the application. follow the steps be low to configure the zlf645 for this mode of operation: 1. provide program code that, w ithin 60 processor clock cycles of the start of code exe- cution after reset, programs bits 6 through b it 4 and bit 1 through 0 of the watchdog timer register (wdtmr) with the time-out se tting required. also ensure bit 3 of the wdtmr register is 1, configuring the wd t for counting once en abled, even with the zlf645 in stop mode. 2. execute the wdt instruction to enab le counting of th e watchdog timer. 3. include a stop instruction after the program code for steps 1 & 2 ab ove, that puts the zlf645 into stop mode when no action is required by the zlf645. once the watchdog timer has been enabled th rough the wdt instruct ion it will begin counting and continue counting even after th e zlf645 has entered st op mode, due to the bit 3 of the wdtmr register being 1. once the wdt has reached its time-out value, it will initiate a reset condition that takes the zlf645 out of st op mode. this reset condi- tion will not cause the wdtmr register to be reset and it will retain its previous program- ming. upon completion of the reset the wdt will enter a di sabled state and stop counting. execution of a new wdt instruction is necessary to cause the watchdog timer to reset to its start count state and to start counting again. it is important to note that if a time-out of the watchdog timer occurs with stop mode in active, the reset generated will cause a reset of the wdtmr register and it will not retain its previously programmed value. in either case of stop mode being active or inactive during watchdog timer time-out, the wdt will go to a disabled st ate upon completion of reset. reset/stop mode recovery status read-only bit smr[7]=0, if the previous reset was initiated by a power-on reset (includ- ing voltage brownout or wdt resets). smr[7]=1 , if the previous reset was initiated by a stop mode recovery. a power-on, voltage brow nout, or wdt reset restores all registers to their power-on reset defaults. a stop mode recovery restores most registers to their power-on reset defaults. register bits not re set by a stop mode recovery are highlighted in grey in the register tables. register bit smr[7] is set to 1 instead of reset by a stop mode recovery. fast stop mode recovery smr[5] can be cleared to 0 before enteri ng stop mode to bypass the default t por reset timer on stop mode recovery. see voltage brownout standby on page 139. ? if smr[5]=0, the stop mode recovery source mu st be kept active for at least 10 input clock periods (tpc). downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 144 s mr[5] must be set to 1 if using a crystal or resonator clock source. the t por delay allows the clock source to stabilize before executing instructions. stop mode recovery interrupt software can set register bit smr4[4] = 1 to en able routing of stop mode recovery events to irq1 and to port 3, pin 3. in this configur ation, if an irq1 interru pt occurs, register bit p3[3] = 0 indicates that a stop mo de recovery event is occurring. stop mode recovery event sources any port 2 or port 3 input pin can be configured to generate a stop mode recovery event, either individually or in various logical combinations. the zlf645 mcu provides the following registers for stop mode recovery source configuration and status: smr register selects one port 3, pin 1C3 pin state or one of three port 2 pin logical combinations to generate an event when a defined 0 or 1 level occurs. smr1 register configures one or more port 2 input pins (0C7) to latch the latest read or write value and generate an event when the pin state changes. smr2 register selects one of seven port 2 and 3 pin logical combinations to generate an event when a defined 0 or 1 level occurs. smr3 register configures one or more port 3 input pins (0C3) to latch the latest read or write value and generates an event when the pin state changes. smr4 register enables routing of smr events to irq1. indicates whether port data has been latched for smr1 or smr3 event monitoring, and whether the latch was on a port read or write. a stop mode recovery event occurs if any of the sources defined in the smr, smr1, smr2, and smr3 registers are active. smr register events the smr register function is si milar to the standard stop m ode recovery feature used in previous z8 ? cpu-compatible parts. register bits smr[4:2] are set to select one of six event modes, as displayed in figure 44 on page 145. the output of the corresponding logic is compared to the state of smr[6]; when th ey are the same, a stop mode recovery event is generated. if smr[4:2]=000, no event source is selected by smr. the state smr[4:2]=001 is reserved and selects no event in this device. the logic config- ured by the smr register ignores any port pins that are configured as output or selected as source pins in registers smr1 or smr3 . the smr register is summarized in table 69 on page 146. note: downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 145 figure 44. smr register-controlled event sources v cc p31p32 p27 p20p23 p20 p27 p33 smr[4:2] = 010 smr[4:2] = 011 smr[4:2] = 100 smr[4:2] = 101 smr[4:2] = 110 smr[4:2] = 111 smr[6] smr smr1 smr2 smr3 p3m[1] orsmr4[4] 0 1 to irq1 and p0[3] to reset and wdt circuitry (active low) this smr register logic ignores any pin configured as an output in the p2m or p3m registers or as a source in the smr1 or smr3 registers. smr[4:2] = 000 downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 146 [ table 69. stop mode recovery register (smr) bit 7 6 5 4 3 2 1 0 field stop flag stop mode recovery level stop delay stop mode recovery source reset time reduction sclk/tclk divide-by-16 reset 00 1 0 0 00 0 r/w rw w w w ww w address bank f: 0bh; linear: f0bh bit position value description [7] ? 01 stop flag indicates whether last startup was power-on reset or stop mode recovery. a write to th is bit has no effect. power-on reset. stop mode recovery. [6] ? 01 stop mode recovery level selects whether an smr[4:2]-selected smr is initiated by a low or high level at the xor-gate input ? (see figure 44 on page 145). low. high. [5] ? 01 stop delay controls the reset delay after recovery. must be 1 if using a crystal or resonator clock source. off. on. [4:2] ? 000 001 010 011 100 101 110 111 stop mode recovery source specifies a stop mode recovery wake-up source at the xor gate input (see figure 44 on page 145). this value is not changed by a stop mode recovery. the following equations ignore any port pin configured as output or selected in smr1 or smr3. no smr register source selected. reserved. p31. p32. p33. p27. port 2 nor 0C3. port 2 nor 0C7. downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 147 smr1 register events the smr1 register can be used to configure one or more port 2 pins to be compared with a written or sampled reference value and genera te a stop mode recovery event when the pin state differs from the reference value. to configure a port 2 pin as an smr1 event source, ensure it is configured as an input in the p2m register, then set the corresponding smr1 register bit. by default, a stop mode recovery event occurs when the pins state is zero. after a port 2 pin is configured as an smr1 source, any subsequent read from or write to the p2 register latches the read or write valu e for reference. a stop mode recovery event occurs when the pins state differs from the l ast reference value latched. the smr1 source logic is displayed in figure 45 on page 149. the program can read register bits smr4[1:0] to determine whether the port 2 pins trigger a stop mode recovery on a change from the last read value (smr4[1:0]=01), or on a change from the last written value (smr4[1:0] =10). software can cl ear smr4[1:0] to 00 to restore the default behavior (configured pi ns trigger when their state is 0). the smr1 register is summarized in table 70 on page 150. [1] 01 smr short reset time controls whether the devices smr reset period is ? equivalent to the rc oscilla tor based por reset period or whether it depends on the detection of xtal1 clock oscillation. unless smr[5]=1, the smr reset period is equivalent to the devices ? rc oscillator based po r reset period and falls in th e range of 2.5 ms to 10 ms. unless smr[5]=1, the smr reset period falls in a range of a minimum of 2.5 ms from chip power up or a maximum of 2. 5 ms from when the xtal1 clock reaches a peak-to-peak amplit ude of oscillation gr eater than 250 mv. [0] 01 sclk/tclk divide-by-16 select controls a divide-by-16 prescaler of the internal sclk/tclk signal (see internal clock signals (sclk and tclk) on page 135). a power-on reset or stop mode recovery clears this bit to 0. off. on. bit position value description downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 148 after the following example code is executed, a 1 on p20 will wake the part from ? stop mode: after the following example code is executed when the value of p2 is 00h, a 1 on p20 ? will wake the part from stop mode: ld p2m, #%ff ;set port 2 to inputs. srp #%0f ;point to expanded bank f ld smr1, #%01 ;select p20 for smr1. srp #%00 ;point to bank 0 ld p2, #%00 ;write 00h to port 2, so the p20 reference ;value is 0, and a 1 on p20 wakes the part. nopstop ld p2m, #%ff ;set ports to inputs. srp #%0f ;point to expanded bank f ld smr1, #%01 ;select p20 for smr1. srp #%00 ;point to bank 0 ld r6, p2 ;if a 0 is read from port 2, the p20 reference ;value is 0, so a 1 on p20 wakes the part. nopstop downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 149 figure 45. smr1 register-controlled event sources to smr1 individual port 2 pin smr logic, n = 0 _ 7 bit smr1 [ n ] port 2, pin n bit p2[ n ] d q port 2 read/write p33 0 1 p3m[1] or smr4[4] irq1 p20 logic p21 logic p22 logic p23 logic smr smr2 smr3 to reset and wdt circuitry (active low) bit p2m [ n ] p24 logic p25 logic p26 logic p27 logic smr1 register p3, bit 3 downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 150 this register is not reset after a stop mode recovery. smr2 register events the smr2 register function is similar to the st andard stop mode recovery feature used in previous z8 cpu-compatible parts. register bits smr2[4:2] are set to select one of seven event modes, as displayed in figure 46 . the output of the corresponding logic is ? compared to the state of smr2 [6]; when they are the same, a stop mode recovery event is generated. if smr2[4:2 ]=000, no event source is selected by smr2. table 70. stop mode recovery register 1 (smr1) bit 7 6 5 4 3 2 1 0 field p27 stop select p26 stop select p25 stop select p24 stop select p23 stop select p22 stop select p21 stop select p20 stop select reset 00000000 r/w wwwwwwww address bank f: 0ch; linear: f0ch bit position value description [7] ? 01 p27 not selected. p27 selected as an smr source. [6] ? 01 p26 not selected. p26 selected as an smr source. [5] 0 1 p25 not selected. p25 selected as an smr source. [4] 0 1 p24 not selected. p24 selected as an smr source. [3] 0 1 p23 not selected. p23 selected as an smr source. [2] 0 1 p22 not selected. p22 selected as an smr source. [1] 0 1 p21 not selected. p21 selected as an smr source. [0] 0 1 p20 not selected. p20 selected as an smr source. note: downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 151 the logic configured by the smr2 register igno res any port pins that are configured as an output, or that are selected as source pins in registers smr1 or smr3. the smr2 register is summarized in table 71 on page 152. figure 46. smr2 register-controlled event sources v cc p20 p31 p31 smr2[4:2] = 001 smr2[4:2] = 011 smr2[4:2] = 100 smr2[4:2] = 101 smr2[4:2] = 110 smr2[4:2] = 111 smr2[6] smr2 smr smr1 smr3 p3m[1] or smr4[4] 0 1 to irq1 and p0[3] to reset and wdt circuitry (active low) this smr2 register logic ignores any pin configured as an output in the p2m or p3m registers or as a source in the smr1 or smr3 registers. smr2[4:2] = 000 p31 p32p33 p20 p21 p22 p31p32 p33 p00 p07 p31 p32 p33 p00 p07 smr2[4:2] = 010 p23 p20 p27 p32 p33 p32p33 p33 downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 152 this register is not reset after a stop mode recovery. smr3 register events the smr3 register can be used to configure one or more of port 3, pins 0C3 to be ? compared to a written or sampled referen ce value and generate a stop mode recovery event when the pin state diff ers from the reference value. table 71. stop mode recovery register 2 (smr2) bit 7 6 5 4 3 2 1 0 field reserved stop mode recovery level 2 reserved stop mode recovery source reserved reset x0x 0 0 0 x x r/w w www address bank f: 0dh; linear: f0dh bit position value description [7] reserved read is undefined; write must be 0. [6] ? 01 stop mode recovery level 2 selects whether an smr2[4:2]-selected smr is initiated by a low or high level at the xor-gate input (see figure 46 on page 151). low. high. [5] reserved read is undefined; must be written to 1. [4:2] 000 001 010 011 100 101 110 111 stop mode recovery source specifies a stop mode recovery wake-up source at th e xor gate input (see figure 46 on page 151). additional sources can be selected by smr, smr1, and smr3 registers. if more than one source is selected, any selected source event causes a stop mode recovery. the followin g equations ignore any port pin that is selected in register smr1 or configured as an output. no smr2 register source selected. nand of p23:p20. nand of p27:p20. nor of p33:p31. nand of p33:p31. nor of p33:p31, p00, p07. nand of p33:p31, p00, p07. nand of p33:p31, p22:p20. [1:0] reserved read is undefined; write must be 00b. note: downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 153 to configure a port 3 input pin as an smr3 event source set the corresponding smr3 ? register bit. by default, a stop mode recove ry event occurs when the pins state is zero. after a port 3 pin is configured as an smr3 source, any subsequent read from or write to the p2 register latches the read or writte n value for reference. a stop mode recovery event occurs when the pins state differs from the last reference valu e latched. the smr3 source logic is displayed in figure 47 . the program can read register bits smr4[3:2] to determine whether the port 3 pins trigger a stop mode recovery on a change from the last read value (smr4[3:2]=01), or on a change from the last written value (smr4[3:2] =10). software can cl ear smr4[3:2] to 00 to restore the default behavior (configured pins trigger when their state is 0). the smr3 register is summarized in table 69 on page 146. after the following example code is executed, a 1 on p30 will wake the part from stop mode. after the following example code is executed when the value of p3 is 00h, a 1 on p30 will wake the part from stop mode. ld smr3, #%01 ;select p30 from smr3. ld p3, #%00 ;write 00h to port 3, so the p30 reference ;value is 0, and a 1 on p30 wakes the part. nopstop ld smr3, #%01 ;select p30 for smr3. ld r6, p3 ;if a 0 is read from port 3, the p30 reference ;value is 0, so a 1 on p30 wakes the part. nopstop downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 154 figure 47. smr3 register-controlled event sources to smr3 individual port 3 pin smr logic, n = 0 _ 3 bit smr3 [ n ] port 3, pin n bit p3[ n ] d q port 3 read/write p33 0 1 p3m[1] or smr4[4] to irq1 and p0[3] p30 logic p31 logic p32 logic p33 logic smr3 smr smr1 smr2 to reset and wdt circuitry (active low) downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 155 this register is not reset after a stop mode recovery. table 72. stop mode recovery register 3 (smr3) bit 7 6 5 4 3 2 1 0 field p 3 3 s m r select p32 smr select p31 smr select p30 smr select reset xxxx 0 0 0 0 r/w wwww address bank f: 0eh; linear: f0eh bit position value description [7:4] reserved reads undefined; must be written to 1. [3] ? 01 p33 not selected. p33 smr source selected. [2] ? 01 p32 not selected. p32 smr source selected. [1] ? 01 p31 not selected. p31 smr source selected. [0] 0 1 p30 not selected. p30 smr source selected. note: downloaded from: http:///
19-4572; rev 0; 4/09 reset/ stop mode recovery status zlf645 series flash mcus product specification 156 stop mode recovery register 4 the stop mode recovery register 4 (see table 73 ) enables the smr interrupt source and indicates the reference value stat us for registers smr1 and smr3. this register is not reset after a stop mode recovery. table 73. stop mode recovery register 4 (smr4) bit 7 6 5 4 3 2 1 0 field reserved smr irq enable port 3 smr status port 2 smr status reset xxx 0 0000 r/w r/w r/w r/w r/w r/w address bank f: 0ah; linear: f0ah bit position value description [7:5] reserved reads are undefined; must write 000b. [4] 01 smr irq enable if p3m[1]=0, smr events do not generate an interrupt. smr events generate an interrupt on irq1. [3:2] ? 0001 10 11 port 3 smr status no read or write of the p3 register occurs. p3 read occurs; used as smr3 reference. p3 write occurs; used as smr3 reference. reserved. [1:0] ? 0001 10 11 port 2 smr status no read or write of the p2 register occurs. p2 read occurs; use p2 read as smr1 reference. p2 write occurs; use p2 write as smr1 reference. reserved. note: downloaded from: http:///
19-4572; rev 0; 4/09 z8 lxmc cpu programming summary zlf645 series flash mcus product specification 157 z8 lxmc cpu programming summary the following sections provide a summary of information useful for programming the z8 lxmc cpu included in this device. for more details on the z8 lxmc cpu and its instruction set, refer to z8 ? lxmc cpu core user manual (um0215) . addressing notation table 74 summarizes z8 lxmc cpu addressing modes and symbolic notation. the text variable n represents a decimal number; aa represents a hexadecimal address; and label represents a label defined elsewhere in the assembly source. in reference notation, only lowercase is used to distin guish 4-bit addressed working ? registers (r1, r2) from 8-bit addressed registers (r1, r2). the numerals 1 and 2, ? respectively, indicate whether the register is used for destination or source addressing. . table 74. symbolic notation for operands symbol assembly ? operand description cc C condition code cc represents a condition code mnemonic. see condition codes on page 161. im # n immediate data im represents an immediate data value, prefixed by # in assembly language where n = 0 to 255. the immediate value follows the instruction opcode in program memory. r1r2 r n working register r1 or r2 represents the name, r n , of a working register, where n = 0, 1, 2,..., 15. the equivalent 12-bit address is {rp[3:0], rp[7:4], n }. rr1 rr2 rr n working register pair rr1 or rr2 represents the name, r n , of a working register pair, where n = 0, 2, 4,..., 14. the equivalent 12-bit address is {rp[3:0], rp[7:4], n }. r1r2 % aa register r1 or r2 represents an 8-bit register address. for addresses 00hCdfh or ? f0hCffh , the equivalent 12-bit address is {rp[3:0], % aa }. for addresses ? e0hCefh (escaped mode), the equivalent 12-bit address is ? {rp[3:0], rp[7:4], % aa [3:0]}. downloaded from: http:///
19-4572; rev 0; 4/09 addressing notation zlf645 series flash mcus product specification 158 rr1 rr2 % aa register pair (8-bit address) rr1 or rr2 represents the 8-bit address of a register pair. for addresses ? 00hCdfh or f0hCffh , the equivalent 12-bit address is {rp[3:0], % aa }. ? for addresses e0hCefh (escaped mode), the equivalent 12-bit address is ? {rp[3:0], rp[7:4], % aa [3:0]}. ir1 ir2 @r n indirect working register ir1 or ir2 represents the name a working register, r n, where n = 0, 1, 2,..., 15. @ indicates indirect working register addressing using an 8-bit effective address contained in the specified working register. the accessed registers equivalent 12-bit address is {rp[3:0], 8-bit effective address }. irr1 irr2 @rr n indirect working register pair irr1 or irr2 represents the name of a working register pair, rr n, where n = 0, 2, 4,..., 14. @ indicates indirect working register addressing using an effective address in the specified working regi ster pair. depending on the instruction, the effective address is in the register file (12-bi t address) or program/constant memory ? (16-bit address). ir1 ir2 @% aa indirect register ir1 or ir2 represents the 8-bit address of a register. @ indicates indirect register addre ssing using an 8-bit effective address contained in the specified r egister. the accessed registers equivalent 12-bit address is {rp[3:0], 8-bit effective address }. irr1 @% aa indirect register pair irr1 represents the 8-bit address of a register. @ indicates indirect register addressing with a 16-bit effective address (in program memory) contained in the specified register pair. x(r1)x(r2) % aa (r n ) indexed (x) addressing x represents the 8-bit base address to which the offset is added. r1 or r2 represents the name, r n , of a working register containing the 8-bit signed offset. the 8-bit effective address is the sum of x and the contents of working register r n . the accessed registers eq uivalent 12-bit address is ? {rp[3:0], 8-bit effective address }. table 74. symbolic notation for operands (continued) symbol assembly ? operand description downloaded from: http:///
19-4572; rev 0; 4/09 addressing notation zlf645 series flash mcus product specification 159 table 75 lists additional symbols that are used throughout the inst ruction set summary. da label direct address (jp, call) in a jp or call operand, da is a 16-bit program memory address in the range of 0000h to ffffh . da replaces the contents of the program counter for execution to continue at a new location in program memory. in assembly source, the address is represented as a label. ra label relative address (jr, djnz) ra is a signed 8-bit program memory offset in the range +127 to C128, relative to the address of the next instruction in program memory. in a jr or djnz operation, ra is added to the program counter to cause execution to continue at a new location in program memory. in assembly source, the jump address is represented as an absolute label, and the assembler calculates ra. table 75. additional symbols symbol definition dst destination operand src source operand @ indirect address prefix c carry flag sp stack pointer value pc program counter flags flags register rp register pointer # immediate operand prefix b binary number suffix % hexadecimal number prefix h hexadecimal number suffix ? assignment of a value. for example, dst ? dst + src indicates the result is stored in the destination table 74. symbolic notation for operands (continued) symbol assembly ? operand description downloaded from: http:///
19-4572; rev 0; 4/09 flags register zlf645 series flash mcus product specification 160 flags register the flags register (see table 76 ) informs the current status of the z8 ? cpu. it contains six bits of status information. ? exchange of two values ~ ones complement unary operator table 76. flags register (flags) bit 7 6 5 4 3 2 1 0 field c z s o d h f1 f2 reset xxxxxxxx r/w r/w r/w r/w r/w r/w r/w r/w r/w address bank independent: fch; linear: 0fch bit position value description [7] 01 carry flag (c) set when the result of an arithmetic operation generates a carry out of or a borrow into the high-order bit (bit 7) of the result. also used in rotate and shift instructions. flag clear flag set [6] 01 zero flag (z) set when the result of an arithmetic operation is 0. flag clear flag set [5] 01 sign flag (s) stores the value of the most significant bi t (msb) following an arithmetic, logical, rotate, or shift instruction. flag clear flag set [4] 01 overflow flag (o) set when the result of an arithmetic operation is greater than 127. flag clear flag set table 75. additional symbols (continued) symbol definition downloaded from: http:///
19-4572; rev 0; 4/09 condition codes zlf645 series flash mcus product specification 161 condition codes the c, z, s, and v fl ags control the operation of the co nditional jump (jp cc and jr cc) instructions. sixteen frequently u seful functions of the flag settings are encoded in a 4-bit field called the c ondition code (cc). table 77 summarizes the condition codes. some binary condition codes can be created using more than one assembly code mnemonic. the result of the flag test operation dete rmines if the conditional jump executes. [3] 01 decimal adjust flag (d) used for binary-coded decimal (bcd) arithmetic. flag clear flag set [2] 01 half carry flag (h) set when a carry out of or borrow into bit 3 of an arithmetic operation occurs. flag clear flag set [1] 01 user flag 1 (f1) available to software for use as a general-purpose bit. bit clear bit set [0] 01 user flag 2 (f2) available to software for use as a general-purpose bit. bit clear bit set table 77. condition codes binary hex assembly mnemonic definition flag test operation 0000 0 f always false C 0001 1 lt less than (s xor v) = 1 0010 2 le less than or equal (z or (s xor v)) = 1 0011 3 ule unsigned less than or equal (c or z) = 1 0100 4 ov overflow v = 1 0101 5 ml minus s = 1 0110 6 z zero z = 1 0110 6 eq equal z = 1 bit position value description downloaded from: http:///
19-4572; rev 0; 4/09 condition codes zlf645 series flash mcus product specification 162 0111 7 c carry c = 1 0111 7 ult unsigned less than c = 1 1000 8 t (or blank) always true C 1001 9 ge greater than or equal (s xor v) = 0 1010 a gt greater than (z or (s xor v)) = 0 1011 b ugt unsigned greater than (c = 0 and z = 0) 1100 c nov no overflow v = 0 1101 d pl plus s = 0 1110 e nz non-zero z = 0 1110 e ne not equal z = 0 1111 f nc no carry c = 0 1111 f uge unsigned greater than or equal c = 0 table 77. condition codes (continued) binary hex assembly mnemonic definition flag test operation downloaded from: http:///
19-4572; rev 0; 4/09 electrical characteristics zlf645 series flash mcus product specification 163 electrical characteristics absolute maximum ratings a stress greater than listed in table 78 may cause permanent damage to the device. functional operation of the device at any condition outside tho se indicated in the ? operational sections of these specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. for improved ? reliability, unused inputs must be tied to one of the supply voltages (v dd or v ss ). table 78. absolute maximum ratings parameter min max units ambient temperature under bias 0 +70 c storage temperature C65 +150 c voltage on any pin with respect to v ss *C 0 . 3 + 4 . 0 v voltage on v dd pin with respect to v ss C0.3 +3.6 v maximum current on input and/or inactive output pin C5 +5 a maximum output current from active output pin C25 +25 ma maximum current into v dd or out of v ss 7 5m a * this voltage applies to all pins except v dd , p32, and p33. downloaded from: http:///
19-4572; rev 0; 4/09 standard test conditions zlf645 series flash mcus product specification 164 standard test conditions the characteristics listed in this product spec ification apply for stan dard test conditions. all voltages are referenced to ground. positive current flow s into the referenced pin ? (see figure 48 ). capacitance table 79 lists the capacitance. figure 48. test load diagram table 79. capacitance parameter maximum input capacitance 12 pf output capacitance 12 pf i/o capacitance 12 pf note: t a = 25 c, v cc = gnd = 0 v, f = 1.0 mhz, unmeasured pins return to gnd. this voltage applies to all pins except v dd , p32, and p33. from output under test 150 pf i downloaded from: http:///
19-4572; rev 0; 4/09 dc characteristics zlf645 series flash mcus product specification 165 dc characteristics table 80 describes the direct current (dc) characteristics of the zlf645 flash mcu. table 80. dc characteristics symbol parameter v cc t a = 0 o c to +70 o c units conditions min typ max v cc supply voltage 1 1 . 93 . 6v s e e note 5 . v ch clock input high voltage 1.9C3.6 0.8 v cc v cc + 0.3 v driven by external clock generator v cl clock input low voltage 1.9C3.6 v ss C0.3 0.4 v driven by external clock generator v ih input high voltage 1.9C3.6 0.7 v cc v cc + 0.3 v v il input low voltage 1.9C3.6 v ss C0.3 0.2 v cc v v oh1 output high voltage 1.9C3.6 v cc C0.4 v i oh = -0.5 ma v oh2 output high voltage (p36, p37, p00, and p01) 1.9C3.6 v cc C0.8 v i oh = -7 ma v ol1 output low voltage 1.9C3.6 0.4 v i ol = 4.0 ma v ol2 output low voltage (p00, p01, p36, and p37) 1.9C3.6 0.8 v i ol = 10 ma v offset comparator input offset voltage 1.9C3.6 25 mv v ref comparator reference voltage 1.9C3.6 0 v cc -1.75 v i il input leakage 1.9C3.6 -1 1 ? av in = 0 v, v cc ; pull-ups disabled i il1 input leakage ir amp (p31) 1.9C3.6 -2.5 -12 ? av in = 0 v, ir amp enabled i ol output leakage 1.9C3.6 -1 1 ? av in = 0 v, v cc i cc supply current 2, 3 1.9 1 2 ma see note 7 . 3.6 2 4 ma 1.9 2 3 ma see note 8 . 3.6 4 6 ma downloaded from: http:///
19-4572; rev 0; 4/09 dc characteristics zlf645 series flash mcus product specification 166 i cc1 standby current 2, 3 (halt mode) 1.9 0.7 1.6 ma v in = 0 v, v cc see note 7 . 3.6 1.2 2.0 ma 1.9 0.9 2 ma v in = 0 v, v cc see note 8 . 3.6 2 3 ma i cc2 standby current 4 (stop mode) 1.9 1.6 8 a v in = 0 v, v cc wdt is not running 3.6 1.8 10 a 1.9 5 20 a v in = 0 v, v cc wdt is running 3.6 8 30 a i lv standby current 5 (low voltage) 1 . 26 ? a measured at 1.3 v v bo v cc low voltage protection 1.8 1.85 1.9 v v lvd v cc low voltage detection 2 . 32 . 42 . 5v v hvd v cc high voltage detection 2 . 7v t oniramp wake-up time from disabled mode 1.9C3.6 20 ? s table 80. dc characteristics (continued) symbol parameter v cc t a = 0 o c to +70 o c units conditions min typ max downloaded from: http:///
19-4572; rev 0; 4/09 dc characteristics zlf645 series flash mcus product specification 167 i detlo ir amp current input guaranteed to be detected as a 0 (see note 6 ) 1.9C3.6 10 ? a ir amp enabled i dethi ir amp current input guaranteed to be detected as a 1 (see note 6 ) 1.9C3.6 100 ? a ir amp enabled notes 1. maxim ? recommends adding a filter capacitor (minimum 0.1 ? f), physically close to v dd and v ss if operating ? voltage fluctuations are anticipa ted, such as those resulting from driving an infrared led. 2. all outputs unloaded, inputs at rail. 3. cl1 = cl2 = 100 pf. 4. oscillator stopped. 5. oscillator stops when v dd falls below v bo limit. 6. for reference, under typical process, 25 c temperature, and a voltage of 2.8 v, the voltage that would be seen at p31 under an input current of 10 ua or 100 ua would be ~480 mv or .560 mv, respectively. 7. 8.0-mhz xtal1 input clock frequ ency with 4-mhz system clock 8. 8.0-mhz xtal1 input clock frequ ency with 8-mhz system clock table 80. dc characteristics (continued) symbol parameter v cc t a = 0 o c to +70 o c units conditions min typ max downloaded from: http:///
19-4572; rev 0; 4/09 ac characteristics zlf645 series flash mcus product specification 168 ac characteristics figure 49 and table 81 lists the alternating current (a c) characteristics of zlf645 flash mcu. figure 49. ac timing diagram clock 1 3 4 8 2 2 3 t in irq n 6 5 7 7 11 clock setup 9 stop-mode recovery source 10 downloaded from: http:///
19-4572; rev 0; 4/09 ac characteristics zlf645 series flash mcus product specification 169 table 81. clock, reset, timers, and smr timing no symbol parameter v cc t a = 0 o c to +70 o c 8.0 mhz units wdtmr (bits 6, 5, 4, 1, 0) min max 1t p c input clock period 1 1.9C3.6 121 dc ns 2t r c, t f c clock input rise and fall times 1 1.9C3.6 25 ns 3t w c input clock width 1 1.9C3.6 37 ns 4t w t in l timer input ? low width 1 1.9 100 ns 3.6 70 ns 5t w t in h timer input high width 1 1.9C3.6 3t p c 6t p t in timer input period 1 1.9C3.6 8t p c 7t r t in , t f t in timer input rise and fall timers 1 1.9C3.6 100 ns 8t w il interrupt request ? low time 1,2 1.9 100 ns 3.6 70 ns 9t w ih interrupt request input high time 1,2 1.9C3.6 5t p c 10 t wsm stop mode recovery width spec 1.9C3.6 12 3 10 t p c 4 n s 11 t ost oscillator ? startup time 4 1.9C3.6 5t p c 12 t wdt watchdog timer delay time 1.9C3.6 5 ms 0, 0, 0, 0, 0 1.9C3.6 10 ms 0, 0, 0, 0, 1 1.9C3.6 20 ms 0, 0, 0, 1, 0 1.9C3.6 80 ms 0, 0, 0, 1, 1 1.9C3.6 320 ms 0, 0, 1, x, x 1.9C3.6 1, 280 ms 0, 1, 0, x, x 1.9C3.6 5, 120 ms 1, 0, 0, x, x downloaded from: http:///
19-4572; rev 0; 4/09 ac characteristics zlf645 series flash mcus product specification 170 13 t por power-on reset 1.9C3.6 2.5 10 5 ms 14 f iramp frequency of input signal for ir amplifier 0 5 0 0 k h z notes 1. timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. 2. interrupt request through port 3 (p33:p31). 3. smr C bit 5 = 1. 4. smr C bit 5 = 0. 5. if bit 1 of the smr register is programmed to 1, th is value is 2.5 ms as measured from the time the ? oscillator input to xtal1 reaches a peak to peak voltage oscillation of at least 300 mv. table 82. flash memory electrical characteristics and timing t a = 0 o c to +70 o c 8.0 mhz no symbol parameter min max units condition 1i flp flash memory programming current 1 0m a 2i fle flash memory page/mass erase current 6m a 3i rd flash dynamic read current 420 a assumes reads every clock cycle with a 1 mhz clock 4v flpe flash memory program/ erase voltage 2.3 3.6 v 5v flr flash memory read voltage 1.8 3.6 v 6t prog flash programming time 30 60 us 7 tpe flash page erase time 10 ms 8 tme flash mass erase time 10 ms 9 tdr flash data retention time 10 years temp=25 o c 10 fen flash program/erase endurance 20,000 cycles table 81. clock, reset, timers, and smr timing (continued) no symbol parameter v cc t a = 0 o c to +70 o c 8.0 mhz units wdtmr (bits 6, 5, 4, 1, 0) min max downloaded from: http:///
19-4572; rev 0; 4/09 flash option bits zlf645 series flash mcus product specification 171 flash option bits programmable flash option bits allow user c onfiguration of certain aspects of zlf645 mcu functionality. this configuration data is stored in the flash memory information block and then read into option byte shadow registers during the last portion of the zlf645 mcus reset period. features available for control thro ugh the flash option bits include: port 0 low nibble pull-ups port 0 high nibble pull-ups port 1 low nibble pull-ups port 1 high nibble pull-ups port 2 pull-ups port 3 low nibble pull-ups port 4 pull-ups wdt always enabled flash protect entire main memory flash protect lower half main memory xtal1 to system clock (no division enable) 16-bit stack addressiblity enable operation option bit shadow regist er loading by reset for each flash memory option bit, there is an associated option bit shadow register that is used to register the value of the option bit. the output of the option bit shadow registers are used by the zlf645 mcu to enable various features and functions for the zlf645 mcu. each time the flash memory informa tion block option bits are programmed or erased, the device must be reset for the chan ge in zlf645 configuration to take effect. a por or stop mode recovery reset with sm r bit 5 set to 1, load s the option bits from the flash memory to the option bit shadow registers during the last few clock cycles of the reset period. in some cases, in order to provide a required value before being loaded, the option bit shadow registers are reset to a predefined value on the start of the reset period. downloaded from: http:///
19-4572; rev 0; 4/09 operation zlf645 series flash mcus product specification 172 the option bit shadow registers are part of the zlf645s register file and are accessible for read/write access. user option bit locations in flash memory the user option bits are located in the upper two bytes of the information block, address ffh and feh. user option bit shadow register access except for bits 0 and 1 of the user opti on byte 1 shadow register, the cpu has full ? read/write access to all the user option byte shadow registers at the address locations given in register tables for each register. user option byte 0 and option byte 0 shadow ? register definitions this option byte allows user control over the enabling of the zlf645s i/o pull-ups and the conditions under which the devices watc hdog timer is enabled. for its associated shadow registers, until the registers are load ed with their corresponding option bit values, their outputs will be in an unknown state. table 83. user option byte 0 (opt0) bit 7 6 5 4 3 2 1 0 field wdt p4pu p3pu p2pu p1hpu p1lpu p0hpu p0lpu erased state 11111111 flash address flash memory information area address: feh bit position value description [7] 10 wdtwatchdog timer enable wdt = 1: wdt is enabled by wdt instruction only. ? wdt = 0: wdt is always enabled. [6:0] p4pu through p0lpugpio pin pull-up enables p4pu = 1: port 4 pull-ups disabled. ? p4pu = 0: port 4 pull-ups enabled. p3pu = 1: port 3 pull-ups disabled. ? p3pu = 0: port 3 pull-ups enabled. downloaded from: http:///
19-4572; rev 0; 4/09 operation zlf645 series flash mcus product specification 173 table 84. user option byte 0 shadow register (opt0sr) user option byte 1 and option byte 1 shadow register ? definitions user option byte allows the enabling of vari ous features including protecting the flashs main memory from read operations through either of the zlf645s flash access inter- faces. for its associated shadow registers, un til the registers are loaded with their corre- sponding option bit values, their outp uts will be in an unknown state. table 85 describes user option byte 1 function. this byte can be programmed and erased (by page 3 erase) only through the icp. during device power-on reset, bit 1 and bit 0 value of this flash option byte are sampled into flip-flops, whose outputs control the flash memory protect function. user codes can read the flip-flop values, by reading from a uni quely assigned peripheral register address. user codes cannot over-write the flip-flop values to change this flash memory protect function. p2pu = 1: port 2 pull-ups disabled. ? p2pu = 0: port 2 pull-ups enabled. p1hpu = 1: port 1 high nibble pull-ups disabled ? p1hpu = 0: port 1 high nibble pull-ups enabled. p1lpu = 1: port 1 low nibble pull-ups disabled. ? p1lpu = 0: port 1 low nibble pull-ups enabled. p0hpu = 1: port 0 high nibble pull-ups disabled. ? p0hpu = 0: port 0 high nibble pull-ups enabled. p0lpu = 1: port 0 low nibble pull-ups disabled. ? p0lpu = 0: port 0 low nibble pull-ups enabled. bit 7 6 5 4 3 2 1 0 field wdt p4pu p3pu p2pu p1hpu p1lpu p0hpu p0lpu reset state xxxxxxxx cpu access (r/w) r/w r/w r/w r/w r/w r/w r/w r/w register address (r/w) bank d: 0eh; linear: d0eh note: note: downloaded from: http:///
19-4572; rev 0; 4/09 operation zlf645 series flash mcus product specification 174 table 85. user option byte 1 (opt1) bit 7 6 5 4 3 2 1 0 field reserved 16bitstk divby1 flprot1 flrwp erased state 1111111 1 flash address flash memory information area address: ffh bit position value description [7:4] reserved must be written 1. [3] 10 16bitstk 16 bit stack pointer addressiblity enable the zlf645 is enabled for 8-bits of stack pointer addressiblity allowing usage of bank 0 only of the devices general-purpose ram space as the cpu stack. the zlf645 is enabled for 16-bits of st ack pointer addressiblity allowing usage of all of the devices general-pu rpose ram space as the cpu stack. [2] 10 divby1 system clock divide by 1 enable if smr register bit 0 is also programmed to 0, the system clock frequency is equal to the external clock frequency input on the xtal1 pin divided by 2. if smr register bit 0 is also programmed to 0, the system clock frequency is equal to the external clock frequency input on the xtal1 pin. [1] 10 flprot1 flash main memory lower half protect the flash main memory and all of information area page 3 can be read, written, and erased by both the flash byte programming interface or through the icp interface as long as flrwp is also 1. reads and writes to the lower half of flash main memory and writes and erasures to information area page 3, by the icp or flash byte programming interfaces is disabled unless, with this bit 0, a main memory mass erase is completed first. a main memory mass er ase causes resetting of this bit value in the option byte 1 shadow regist er to a 1 but does not effect the corresponding flash memory bit. once th e option byte 1 shadow register bit is reset, the icp or flash byte programming interface is allowed full read, write, and erase access to the flash's main memory and to page 3 of the information area and can reset the corresponding flash memory bit. downloaded from: http:///
19-4572; rev 0; 4/09 operation zlf645 series flash mcus product specification 175 table 86. user option byte 1 shadow register (opt1sr) reserved bits when read by the cpu will re turn 0 and when written have no effect. [0] 1 0 flrwp flash main me mory protect flash main memory and information area page 3 can be read, programmed, and erased by both the flash byte programming interface or through the icp interface. reads and writes to the flash main memory and writes and erasures to information area page 3 by the icp or flash byte programming interfaces is disabled unless, with this bit 0, a main memory mass erase is completed first. a main memory mass erase causes resetting of this bit value in the option byte 1 shadow register to a 1 but do es not effect the corresponding flash memory bit. once the option byte 1 sh adow register bit is reset, the icp or flash byte programming interface is allo wed full read, write, and erase access to the flashs main memory and to page 3 of the information area and can reset the corresponding flash memory bit. bit 7 6 5 4 3 2 1 0 field reserved 16bitstk divby1 flprot1 flrwp reset state xxxx x 1 x x cpu access (r/w) r/w r/w r r register address (r/w) bank d: 0fh; linear: d0fh note: downloaded from: http:///
19-4572; rev 0; 4/09 packaging zlf645 series flash mcus product specification 176 packaging figure 50 displays the 20-pin quad flat no-lead (qfn) package for the zlf645 series of flash mcus. figure 50. 20-pin qfn package diagram downloaded from: http:///
19-4572; rev 0; 4/09 packaging zlf645 series flash mcus product specification 177 figure 51 displays the 20-pin shrink small outlin e package (ssop) for the zlf645 series of flash mcus. figure 51. 20-pin ssop package diagram downloaded from: http:///
19-4572; rev 0; 4/09 packaging zlf645 series flash mcus product specification 178 figure 52 displays the 20-pin small outline inte grated circuit (soic) package for the zlf645 series of flash mcus. figure 52. 20-pin soic package diagram downloaded from: http:///
19-4572; rev 0; 4/09 packaging zlf645 series flash mcus product specification 179 figure 53 displays the 20-pin plastic dual inline package (pdip) for th e zlf645 series of flash mcus. figure 53. 20-pin pdip package diagram downloaded from: http:///
19-4572; rev 0; 4/09 packaging zlf645 series flash mcus product specification 180 figure 54 displays the 28-pin shrink small outlin e package (ssop) for the zlf645 series of flash mcus. figure 54. 28-pin ssop package diagram symbol aa1 b c a2 e millimeter inch min max min max 1.730.05 1.68 0.25 5.20 0.65 typ 0.0910.07 7.65 0.63 1.86 0.0256 typ 0.1310.20 1.737.80 5.30 1.990.21 1.78 0.75 0.0680.002 0.066 0.010 0.205 0.0040.397 0.301 0.025 0.0730.005 0.068 0.209 0.0060.402 0.307 0.030 0.0780.008 0.070 0.015 0.212 0.0080.407 0.311 0.037 0.380.20 10.33 5.38 7.90 0.95 nom nom de h l controlling dimensions: mm leads are coplanar within .004 inches. h c detail a e d 28 15 11 4 seating plane a2 e a q1 a1 b l 0 - 8 detail 'a' downloaded from: http:///
19-4572; rev 0; 4/09 packaging zlf645 series flash mcus product specification 181 figure 55 displays the 28-pin small outline inte grated circuit (soic) package for the zlf645 series of flash mcus. figure 55. 28-pin soic package diagram downloaded from: http:///
19-4572; rev 0; 4/09 packaging zlf645 series flash mcus product specification 182 figure 56 displays the 28-pin plastic dual inline package (pdip) for th e zlf645 series of flash mcus. figure 56. 28-pin pdip package diagram log z downloaded from: http:///
19-4572; rev 0; 4/09 packaging zlf645 series flash mcus product specification 183 figure 57 displays the 48-pin shrink small outline package (ssop) for the zlf645 ? series of flash mcus. figure 57. 48-pin ssop package diagram 20984 05-07-07 m. fone downloaded from: http:///
19-4572; rev 0; 4/09 ordering information zlf645 series flash mcus product specification 184 ordering information table 87 lists the part numbers for zlf645 series of flash mcus and a brief description of each part. table 87. zlf645 flash mcu part numbers description part number flash (kb) ram description zlf645 flash mcu with 512 b ram zlf645s0h2064g 64 512 b ssop 20-pin package zlf645s0h2864g 64 512 b ssop 28-pin package zlf645s0h4864g 64 512 b ssop 48-pin package zlf645s0p2064g 64 512 b pdip 20-pin package zlf645s0p2864g 64 512 b pdip 28-pin package zlf645s0s2064g 64 512 b soic 20-pin package zlf645s0s2864g 64 512 b soic 28-pin package zlf645s0q2064g 64 512 b qfn 20-pin package zlf645s0h2032g 32 512 b ssop 20-pin package zlf645s0h2832g 32 512 b ssop 28-pin package zlf645s0h4832g 32 512 b ssop 48-pin package zlf645s0p2032g 32 512 b pdip 20-pin package zlf645s0p2832g 32 512 b pdip 28-pin package zlf645s0s2032g 32 512 b soic 20-pin package zlf645s0s2832g 32 512 b soic 28-pin package zlf645s0q2032g 32 512b qfn 20-pin package zlf645 flash mcu with 1k ram zlf645e0h2064g 64 1 k ssop 20-pin package zlf645e0h2864g 64 1 k ssop 28-pin package zlf645e0h4864g 64 1 k ssop 48-pin package zlf645e0p2064g 64 1 k pdip 20-pin package zlf645e0p2864g 64 1 k pdip 28-pin package zlf645e0s2064g 64 1 k soic 20-pin package zlf645e0s2864g 64 1 k soic 28-pin package downloaded from: http:///
19-4572; rev 0; 4/09 ordering information zlf645 series flash mcus product specification 185 zlf645e0q2064g 64 1k qfn 20-pin package zlf645e0h2032g 32 1 k ssop 20-pin package zlf645e0h2832g 32 1 k ssop 28-pin package zlf645e0h4832g 32 1 k ssop 48-pin package zlf645e0p2032g 32 1 k pdip 20-pin package zlf645e0p2832g 32 1 k pdip 28-pin package zlf645e0s2032g 32 1 k soic 20-pin package zlf645e0s2832g 32 1 k soic 28-pin package zlf645e0q2032g 32 1k qfn 20-pin package zcrmznice01zemg crimzon ice kit (includes smart cable for zlf645 in-circuit programming) zcrmzn00100kitg crimzon/zlf645 ir development board kit zcrmznice01zacg crimzon/zlf645 20-pin accessory kit zcrmznice02zacg crimzon/zlf645 40-/48-pin accessory kit table 87. zlf645 flash mcu part numbers description (continued) part number flash (kb) ram description downloaded from: http:///
19-4572; rev 0; 4/09 part number description zlf645 series flash mcus product specification 186 part number description maxim ? part numbers consist of a number of components as shown below: zl f645e0h4864g environmental flow ? g = lead free (green part) flash memory 64 = 64 kb 32 = 32 kb number of pins in package ? 48 = 48-pin 28 = 28-pin 20 = 20-pin package type h = ssop p = pdip ? s = soic q = qfn ram size e0 = extended 1k ram s0 = standard 512 b ram family series memory type f = flash low voltage maxim index downloaded from: http:///
19-4572; rev 0; 4/09 index zlf645 series flash mcus product specification 187 indexnumerics 11890 figure title figure 34. resets and wdt 138 12-bit address map 47 16-bit counter/timer circuits 109 20-pin package pins 6, 8, 9 pdip package 179, 183 soic package 178 ssop package 177 28-pin package pins 11, 13, 16 pdip package 182 soic package 181 ssop package 176, 180 32178 figure title figure 17. t8_out in modulo-n mode 104 40203 figure title figure 16. t8_out in single-pass mode 104 60053 table title table 32. stop mode recovery regis- ter 2 155 64329 table title table 37. stop mode recovery regis- ter 4 156 8-bit counter/timer circuits 103 a absolute maximum ratings 163 ac characteristics 168, 169 ac timing 168 active low notation 3 address 12-bit linear 47 notation 157 amplifier, infrared 84 and caution 119 architecture uart 86 asynchronous data 87 b baud rate generator description 93 example 94 interrupt 93 baud rate generator constant register (bcnst) 97, 98 block diagram counter/timer 99 interrupt 128 mcu 4 reset and watch-dog timer 138 uart 86 brown-out, voltage 143 brownout, voltage 139 c capacitance 164 caution stopping timer 104 timer count 103 timer modes 121 timer registers 110 uart transmit 88, 89 characteristics ac 168, 169 dc 165 clock 134 downloaded from: http:///
19-4572; rev 0; 4/09 index zlf645 series flash mcus product specification 188 internal signals 135 comparator inputs 28 outputs 28 condition codes 161 conditions, test 164 connection, power 3 constant memory 41 constant, baud rate 97, 98 counter/timer block diagram 99 capture flowchart 106 input circuit 101 output configuration 27 crystal 134 crystal oscillator pins (xtal1, xtal2) 134, 135 customer support 193 d data format, uart 87 data handling, uart 91 dc characteristics 165 demodulation changing mode 121 flowchart 106, 107 timer 105, 110 demodulation mode flowchart 108 device block diagram 4 features 1 diagram, package 176, 177, 178, 179, 180, 181, 182, 183 divisor, baud rate 97, 98 e electrical characteristics 163 error handling, uart 91 example bcnst register 94 register pointer 45 f fast recovery, stop mode 143 features, device 1 flags register 160 flash option bit configuration - reset 171 flash memory 67, 82 arrrangement 68 byte programming 74 code protection 73 configurations 67 control register definitions 75 flash status register 77 flow chart 72 frequency high and low byte registers 79 mass erase 75 operation 69 operation timing 69 page erase 74 page select register 77, 78 flowchart demodulation mode 106, 107, 108 timer transmit 102 uart receive 92 format, uart data 87 fps register 77, 78 fstat register 77 functional block diagram 4 hh suffix 104 halt mode 143 handshaking, uart 90 iicp architecture 54 auto-baud detector/generator 55 baud rate limits 56 block diagram 54 commands 57 downloaded from: http:///
19-4572; rev 0; 4/09 index zlf645 series flash mcus product specification 189 control register 64 data format 55 debug mode 54 serial errors 56 status register 65 icp commands read icp control register (05h) 59 read icp revision (00h) 58 read icp status register (02h) 59 read program memory (0bh) 60 read program memory crc (0eh) 60 read register (09h) 59 read runtime counter (03h) 59 write icp control register (04h) 59 write program memory (0ah) 59, 61 write register (08h) 59 icp interface 53 infrared learning amplifier 84 input comparator 28 counter/timer 101 timers 100 instruction set summary 162 instruction symbols 159 internal clock 135 interrupt baud rate generator 93 block diagram 128 description 127 mask register 133 priority register 130 request register 130, 131 source 129 stop-mode recovery 144 type 129 uart 90 uart receive 89, 90, 92 uart transmit 88, 90 vector 129 interrupt mask register (imr) 133 interrupt priority register (ipr) 130 interrupt request register (irq) 130, 131 llde and ldei instructions removed 46 ldx, ldxi instruction addresses 47 learning amplifier, infrared 84 linear address 45 load, test 164 low-voltage detection register (lvd) 140 m map program/constant memory 41 register 12-bit 47 register 8-bit 43 register file summary 50 maximum ratings 163 mcu block diagram 4 features 1 memory address, linear 45 program/constant map 41 register 12-bit map 47 register file map 43 register file summary 50 modulo-n mode 104, 110 nnotation addressing 157 operand 157 o operand symbols 157 operation, uart 86 operational description 67, 171 or caution 119 oscillator 134 output comparator 28 timer/counter 112 downloaded from: http:///
19-4572; rev 0; 4/09 index zlf645 series flash mcus product specification 190 timer/counter circuit 113 timer/counter configuration 27 overline, in text 3 overrun, uart 91 p package diagram 176, 177, 178, 179, 180, 181, 182, 183 package information 176 parity, uart data 87 pin description 5 pin function port 0 20 port 2 21, 28 port 3 23 port 3 summary 26 ping-pong mode 111, 112 pins 20-pin package 6, 8, 9 28-pin package 11, 13, 16 polled uart receive 89 polled uart transmit 87 port 0 configuration 20 pin function 20 port 0 mode register (p01m) 31 port 0 register (p0) 32 port 2 configuration 22 pin function 21, 28 port 2 mode register (p2m) 34, 39 port 2 register (p2) 33, 35, 40 port 3 configuration 24 counter/timer output 27 pin function 23 pin function 26 port 3 mode register (p3m) 36 port 3 register (p3) 37 port configuration register (pcon) 28, 30 power connection 3 power management 137 power-on reset timer 139 program memory map 41 programming summary 157 r ratings, maximum 163 register bcnst 98 ctr1 121 ctr3 126 flash high and low byte (ffreqh and fre- eql) 79 flash page select (fps) 77, 78 flash status (fstat) 77 hi16 115 hi8 114 icp control 64 icp status 65 imr 133 ipr 130 irq 130, 131 lo16 116 lo8 115 lvd 140 p0 32 p01m 31 p2 33, 35, 40 p2m 34, 39 p3 37 p3m 36 pcon 28, 30 register pointer register 48 rp 48 smr 146 smr1 150 smr2 152 smr3 155 smr4 156 spl 48, 49 uctl 96, 97 urdata 95 user 48 ust 95 downloaded from: http:///
19-4572; rev 0; 4/09 index zlf645 series flash mcus product specification 191 utdata 95 wdtmr 142 register file 12-bit address 47 address summary 50 description 42 memory map 43 register pointer detail 44 example 45 register pointer register 48 register pointer register (rp) 48 register pointer register (rp) 48 reset block diagram 138 delay bypass 143 features 137 por timer 139 status 143 timer terminal count 119 ssclk signal 135 single-pass mode 104 source interrupt 129 stop mode recovery 144 stop-mode recovery 145, 149, 151 stack 42 stack pointer register (spl) 48, 49 standard test conditions 164 standby, brown-out 139 standby, brownout 143 status reset 143 uart 95 stop bit, uart 91 stop mode fast recovery 143 stop mode recovery register (smr) 146 stop mode recovery register 1 (smr1) 150 stop mode recovery register 2 (smr2) 152 stop mode recovery register 3 (smr3) 155 stop mode recovery register 4 (smr4) 156 stop-mode description 143 recovery events 144, 147, 150, 152 recovery interrupt 144 recovery source 144, 145, 149, 151 recovery status 143 stop-mode recovery register 4 (smr4) 156 suffix, h 104 symbols address 157 instruction 159 operand 157 tt16_out signal modulo-n mode 110 t8_out signal modulo-n mode 104 single-pass mode 104 tclk signal 135 terminal count, reset 119 test conditions 164 test load 164 timer block diagram 99 changing mode 121 description 99 input circuit 100, 101 output circuit 113 output configuration 27 output description 112 reset 139 starting count caution 103 stopping caution 104 t16 demodulation 110 t16 transmit 109 t16_out signal 110 t8 demodulation 105 t8 transmit 101 t8_out signal 104 transmit flowchart 102 transmit versus demodulation mode 121 downloaded from: http:///
19-4572; rev 0; 4/09 index zlf645 series flash mcus product specification 192 timer 16 capture high register (hi16) 115 timer 16 capture low register (l016) 116 timer 16 control register (ctr2) 124 timer 16 high hold register (tc16h) 116 timer 16 low hold register (tc16l) 117 timer 8 and timer 16 common functions register (ctr1) 121 timer 8 capture high register (hi8) 114 timer 8 capture low register (l08) 115 timer 8 control register (ctr0) 119 timer 8 high hold register (tc8h) 117 timer 8 low hold register (tc8l) 118 timer 8/timer 16 control register (ctr3) 126 timing, ac 168 transmit caution, uart 88, 89 transmit mode caution 121 flowchart 102 timer 101, 109 uuart architecture 86 baud rate generator 93 block diagram 86 data and error handling 91 data format 87 interrupts 90 operation 86 overrun error 91 polled receive 89 polled transmit 87 receive interrupt 89, 90, 92 stop bit 91 transmit caution 88, 89 transmit interrupt 88, 90 uart control register (uctl) 96, 97 uart receive/transmit data register (urda- ta/utdata) 95 uart status register (ust) 95 user data register (user) 48 v vector, interrupt 129 voltage brown-out 139, 143 detection 143 detection register 140 w watchdog timer description 141 watchdog timer diagram 138 watchdog timer mode register (wdtmr) 142 xxtal1 pin 134 xtal2 pin 135 z zlr64400 mcu block diagram 4 features 1 downloaded from: http:///
19-4572; rev 0; 4/09 customer support zlf645 series flash mcus product specification 193 customer support for any comments, detail techni cal questions, or reporting problems, please visit maxims technical support at https://support.ma xim-ic.com/micro . downloaded from: http:///

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